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STP200NF04L
STB200NF04L - STB200NF04L-1
N-CHANNEL 40V - 3 mΩ - 120 A TO-220/D²PAK/I²PAK STripFET™ II MOSFET
Table 1: General Features
TYPE STB200NF04L STP200NF04L STB200NF04L-1
s s s
Figure 1: Package
RDS(on) 3.5 mΩ 3.8 mΩ 3.8 mΩ ID 120 A 120 A 120 A
3 1 2
VDSS 40 V 40 V 40 V
TYPICAL RDS(on) = 3mΩ 100% AVALANCHE TESTED LOW THERESHOLD DRIVE
3 1
TO-220
D²PAK
DESCRIPTION This MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” stripbased process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and lesscritical alignement steps therefore a remarkable manufacturing reproducibility. This new improved device has been specifically designed for Automotive applications. APPLICATIONS s HIGH CURRENT, HIGH SWITCHING SPEED
3 12
I²PAK
Figure 2: Internal Schematic Diagram
Table 2: Order Codes
PART NUMBER STP200NF04L STB200NF04L STB200NF04L-1 MARKING P200NF04L B200NF04L B200NF04L PACKAGE TO-220 D²PAK I²PAK PACKAGING TUBE TAPE & REEL TUBE
Rev. 1 April 2005 1/12
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Table 3: Absolute Maximum ratings
Symbol VDS VGDR VGS ID (**) ID IDM (2) PTOT
dv/dt (1)
Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS=20 KΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature
Value 40 40 ± 16 120 120 480 300 2 3.6 1.4 -55 to 175
Unit V V V A A A W W/°C V/ns J °C
EAS (3) Tstg Tj
(1)ISD ≤ 100 A, di/dt ≤ 240 A/µs, VDD ≤ 32 , Tj ≤ TJMAX (2) Pulse width limited by safe operating area. (3) Starting Tj = 25°C, IAR = 50A, VDD = 30V (**) Current limited by Package
Table 4: Thermal Data
TO-220/I²PAK Rthj-case Rthj-pcb (*) Rthja Tl Thermal Resistance Junction-case Thermal Resistance Junction-pcb Thermal Resistance Junction-ambient Max Max Max 62.5 300 0.50 35 --°C D²PAK Unit °C/W °C/W
Maximum Lead Temperature For Soldering Purpose
(*)When mounted on 1 inch² FR4 2oZ Cu
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Test Conditions ID = 250 µA, VGS = 0 Min. 40 1 10 ±100 1 TO-220 I²PAK D²PAK 3.3 3.8 3.0 3.5 4 3.8 4.6 3.5 4.3 Typ. Max. Unit V µA µA nA V mΩ mΩ mΩ mΩ
VDS= Max Rating Zero Gate Voltage Drain Current (VGS = 0) VD = Max Rating, TC= 125 °C Gate-body Leakage Current (VDS = 0) Static Drain-source On Resistance VGS = ± 16V
Gate Threshold Voltage VDS = VGS, ID = 250µA VGS = 10 V, ID = 50 A VGS = 5 V, ID = 50 A VGS = 10 V, ID = 50 A VGS = 5 V, ID = 50 A
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ELECTRICAL CHARACTERISTICS (CONTINUED) Table 6: Dynamic
Symbol gfs (4) Ciss Coss Crss td(on) tr td(off) tf tf(Voff) tf tc Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Turn-off Delay Time Fall Time Cross-over Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 20 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 60 6400 1300 190 37 270 90 80 85 125 160 72 20 28.5 90 Max. Unit S pF pF pF ns ns ns ns ns ns ns nC nC nC
VDD = 20 V, ID = 50 A, RG= 4.7 Ω VGS = 4.5 V (see Figure 16) Vclamp = 32 V, ID = 100 A, RG= 4.7 Ω VGS = 4.5 V (see Figure 17) VDD = 32 V, ID = 100 A, VGS = 4.5 V (see Figure 19)
Table 7: Source Drain Diode
Symbol ISD ISDM (1) VSD (4) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 160 A, VGS = 0 ISD = 100 A, di/dt = 100 A/µs, VDD = 20 V, Tj = 150°C (see Figure 16) 88 240 5.5 Test Conditions Min. Typ. Max. 100 400 1.3 Unit A A V ns nC A
(1) Pulse width limited by safe operating area (4). Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized Breakdown Voltage vs Temperature
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Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform
Figure 16: Switching Times Test Circuit For Resistive Load
Figure 19: Gate Charge Test Circuit
Figure 17: Test Circuit For Inductive Load Switching and .