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ZL50012 Dataheets PDF



Part Number ZL50012
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description Flexible 512-ch Digital Switch
Datasheet ZL50012 DatasheetZL50012 Datasheet (PDF)

www.DataSheet4U.com ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • • • • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation Rate conversion between the ST-BUS inputs and ST-BUS outputs Per-stream ST-BUS input with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s Per-stream ST-BUS output with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s; the output data rate can be different than the input data rate Per-stream h.

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www.DataSheet4U.com ZL50012 Flexible 512-ch Digital Switch Data Sheet Features • • • • 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation Rate conversion between the ST-BUS inputs and ST-BUS outputs Per-stream ST-BUS input with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s Per-stream ST-BUS output with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s; the output data rate can be different than the input data rate Per-stream high impedance control output for every ST-BUS output with fractional bit advancement Per-stream input channel and input bit delay programming with fractional bit delay Per-stream output channel and output bit delay programming with fractional bit advancement Multiple frame pulse outputs and reference clock outputs Per-channel constant throughput delay • • • • • • • Ordering Information ZL50012/QCC ZL50012/GDC 160 Pin LQFP 144 Ball LBGA July 2004 -40°C to +85 °C Per-channel high impedance output control Per-channel message mode Per-channel pseudo random bit sequence (PRBS) pattern generation and bit error detection Control interface compatible to Motorola nonmultiplexed CPUs Connection memory block programming capability IEEE-1149.1 (JTAG) test port 3.3V I/O with 5 V tolerant input • • • • • VDD VSS RESET ODE STi0-15 S/P Converter Data Memory P/S Converter STo0-15 FPi CKi Output HiZ Control Input Timing Connection Memory STOHZ0-15 Microprocessor Interface and Internal Output Timing FPo0 CKo0 FPo1 CKo1 FPo2 CKo2 IC0 - 4 CLKBYPS ICONN0 - 2 Registers APLL Test Port VDD_APLL VSS_APLL D15 - 0 A11 - 0 DTA TMS TDO TCK Figure 1 - ZL50012 Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2004, Zarlink Semiconductor Inc. All Rights Reserved. TRST SG1 TM1 TM2 R/W DS CS TDI ZL50012 Applications • • • • • Small and medium digital switching platforms Access Servers Time Division Multiplexers Computer Telephony Integration Digital Loop Carriers Data Sheet Description The device has sixteen ST-BUS inputs (STi0-15) and sixteen ST-BUS outputs (STo0-15). It is a non-blocking digital switch with 512 64 kb/s channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs. The ST-BUS inputs accept serial input data streams with the data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s on a per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s on a per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers. The ZL50012 has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. 2 Zarlink Semiconductor Inc. ZL50012 Table of Contents Data Sheet Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 ST-BUS Input Data Rate and Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 ST-BUS Input Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.2 Frame Pulse Input and Clock Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.3 ST-BUS Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 ST-Bus Output Data Rate and Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 ST-Bus Output Operation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.2 Frame Pulse Output and Clock Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3 ST-BUS Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.


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