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IDT70T9349L Dataheets PDF



Part Number IDT70T9349L
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description (IDT70T9349L / IDT70T9359) SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Datasheet IDT70T9349L DatasheetIDT70T9349L Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM .eatures: x x x IDT70T9359/49L x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial:7.5/9/12ns (max.) – Industrial: 9ns (max.) Low-power operation – IDT70T9359/49L Active: 225mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and re.

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www.DataSheet4U.com PRELIMINARY HIGH-SPEED 2.5V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM .eatures: x x x IDT70T9359/49L x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial:7.5/9/12ns (max.) – Industrial: 9ns (max.) Low-power operation – IDT70T9359/49L Active: 225mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic x x x x Full synchronous operation on both ports – 4.0ns setup to clock and 0.5ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 2.5V (±100mV) power supply Industrial temperature range (–40°C to +85°C) is available for 66MHz Available in a 100-pin Thin Quad Flatpack (TQFP) and 100pin fine pitch Ball Grid Array (fpBGA) packages. .unctional Block Diagram R/WL UBL CE0L R/WR UBR CE0R CE1L LBL OEL 1 0 0/1 1 0 0/1 CE1R LBR OER FT/PIPEL 0/1 1b 0b b a 1a 0a 0a 1a a b 0b 1b 0/1 FT/PIPER I/O9L-I/O17L I/O0L-I/O8L I/O Control I/O9R-I/O17R I/O Control I/O0R-I/O8R A12L(1) A0L CLKL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A12R(1) A0R CLKR ADSL CNTENL CNTRSTL ADSR CNTENR CNTRSTR 5640 drw 01 NOTE: 1. A 12 is a NC for IDT70T9349. JULY 2002 1 ©2002 Integrated Device Technology, Inc. DSC-5640/1 IDT70T9359/49L High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Preliminary Industrial and Commercial Temperature Ranges Description: The IDT70T9359/49 is a high-speed 8/4K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T9359/49 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 225mW of power. Pin Configurations (1,2,3,4) 06/07/02 Index A9L A10L A11L A12L(1) NC NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VDD FT/PIPEL I/O17L I/O16L VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL VSS VSS ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R 70T9359/49PF PN100-1(5) 100-Pin TQFP Top View(6) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A8R A9R A10R A11R A12R(1) NC NC NC LBR UBR CE0R CE1R CNTRSTR R/WR VSS OER FT/PIPER I/O17R VSS I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R 5640 drw 02 NOTES: 1. A12 is a NC for IDT70T9349. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. I/O9L I/O8L VDD I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L VSS I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VDD I/O7R I/O8R I/O9R I/O10R . 6.42 2 IDT70T9359/49L High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configurations (con't.)(1,2,3,4) 70T9359/49BF BF100(5) 100-Pin fpBGA Top View(6) A2 A3 A4 CNTRSTR 0 6/07/02 A1 A5 A6 A7 A8 A9 A10 A8R B1 A11R B2 UB R B3 Vss B5 Vss B6 B7 Vss I/O13R I/O10R I/O17R B8 B9 B10 B4 A6R C1 A7R C2 A 10R A 12R(1) R/W R C3 C4 C5 OE R PL/FTR I/O12R I/O9R I/O6R C6 C7 C8 C9 C10 A 3R D1 A4R D2 A 5R D3 A9R D4 CE 1R I/O16R I/O15R I/O11R I/O7R I/O3R D5 D6 D7 D8 D9 D10 A0R E1 CLKR E2 A 1R E3 CNTENR F3 A 2R E4 LB R E5 CE 0R I/O14R I/O8R E6 E7 E8 I/O5R I/O1R E9 E10 Vss F1 ADS R F2 A1L F4 ADSL F5 Vss F6 I/O4R F7 I/O2R F8 I/O0R F9 VDD F10 Vss G1 CNTENL H1 CLKL G2 A0L G3 A 3L G4 V DD G5 Vss G6 V DD G7 I/O2L G8 I/O1L G9 I/O0L G10 A4L H2 A 7L H3 UBL H4 H5 Vss I/O13L H6 NC H7 I/O4L H8 Vss H9 I/O3L H10 , A2L J1 A6L J2 A11L J3 CE 0L J4 CNTRST L I/O15L I/O9L J6 J7 I/O7L J8 I/O6L J9 I/O5L J10 J5 A 5L K1 A9L K2 A 12L(1).


HS-1380 IDT70T9349L IDT70T9359


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