K4S561632C

www.DataSheet4U.com K4S561632C CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 Sept. 2001 DataSheet 4 U .com www.DataSheet4U.com K4S561632C Revision History Revision 0.1 (Feb. 15, 2001) Added DC charcteristics. CMOS SDRAM Revision 0.2 (Mar. 06, 2001) Deleted "Preliminary" Changed DC charcteristics Revision 0.3 (Jun 04, 2001) Corrected typo in DC characteristics Revision 0.4 (Sep. 06, 2001) Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 0.4 Sept. 2001 DataSheet 4 U .com www.DataSheet4U.com K4S561632C 4M x 16Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (8K Cycle) Part No. K4...