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MB15F73UL Dataheets PDF



Part Number MB15F73UL
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description ASSP Dual Serial Input PLL Frequency Synthesizer
Datasheet MB15F73UL DatasheetMB15F73UL Datasheet (PDF)

www.DataSheet4U.com Dec. 2000 Edition 2.0 ASSP Dual Serial Input PLL Frequency Synthesizer MB15F73UL n DESCRIPTION The Fujitsu MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250MHz and a 600MHz prescalers. A 64/65 or a 128/129 for the 2250MHz prescaler, and a 8/9 or a 16/17 for the 600MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process is used, as a result a supply current is typically 3.2mA typ. a.

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www.DataSheet4U.com Dec. 2000 Edition 2.0 ASSP Dual Serial Input PLL Frequency Synthesizer MB15F73UL n DESCRIPTION The Fujitsu MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250MHz and a 600MHz prescalers. A 64/65 or a 128/129 for the 2250MHz prescaler, and a 8/9 or a 16/17 for the 600MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process is used, as a result a supply current is typically 3.2mA typ. at 2.7V. The supply voltage range is from 2.4V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA selectable by serial data. The data format is same as the previous one MB15F03SL, MB15F73SP. Fast locking is acheived for adopting the new circuit. The new package(BCC20) decreases a mount area of MB15F73UL more than 30% comparing with the former BCC16(for dual PLL). MB15F73UL is ideally suited for wireless mobile communications, such as GSM and CDMA. n FEATURES • High frequency operation: RF synthesizer : 2250MHz max IF synthesizer : 600MHz max • Low power supply voltage: VCC = 2.4 to 3.6 V • Ultra Low power supply current : ICC = 3.2 mA typ. (VCC = Vp=2.7V, Ta=25°C, SW=0 in RF, IF locking state) • Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA(Vcc=Vp=2.7V, Ta=25°C), Max. 10 µA(Vcc=Vp=2.7V) • Dual modulus prescaler : 2250MHz prescaler(64/65 or 128/129) / 600MHz prescaler(8/9 or 16/17) • Serial input 14-bit programmable reference divider: R = 3 to 16,383 • Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 • On-chip phase comparator for fast lock and low noise • On-chip phase control for phase comparator • Operating temperature: Ta = –40 to 85°C • Sireal data format compatible with MB15F03SL l e Pr n i im . y ar 20-pin, Plastic TSSOP 20-pad, Plastic BCC (LCC-20P-M05) (FPT-20P-M06) 1 www.DataSheet4U.com MB15F73UL n Dec. 2000 Edition 2.0 PIN ASSIGNMENT OSCIN GND 1 2 3 4 5 20 19 18 17 Clock Data LE finRF XfinRF GNDRF VccRF PSRF VpRF DoRF DoIF DoRF VpRF LD/fout finIF XfinIF GNDIF VccIF PSIF VpIF 1 2 3 4 5 6 7 8 9 10 TOP VIEW Data OSCIN GND Clock 20 19 18 17 16 15 14 13 12 11 LE finRF XfinRF GNDRF VCCRF PSRF finIF XfinIF GNDIF VccIF PSIF VpIF DoIF LD/fout TOP 16 VIEW 15 6 7 8 9 10 14 13 12 11 FPT-20P-M06 LCC-20P-M05 2 www.DataSheet4U.com Dec. 2000 Edition 2.0 MB15F73UL n PIN DESCRIPTIONS Pin No. Pin name OSCIN GND finIF XfinIF GNDIF VccIF I/O I I I Descriptions The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for OSC input buffer and the shift registor circuit. Prescaler input pin for the IF-PLL section. Connection to an external VCO should be AC coupling. Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. Ground for the IF-PLL section. Power supply voltage input pin for the IF-PLL section(except for the charge pump circuit), the shift register and the oscillator input buffer. When power is OFF, latched data of IF-PLL is lost. Power saving mode control for the IF-PLL section. This pin must be set at ”L” Power-ON. (Open is prohibited.) PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode Power supply voltage input pin for the IF-PLL charge pump. Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Lock detect signal output(LD)/ phase comparator monitoring outut (fout). The output signal is selected by a LDS bit in a serial data. LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power supply voltage input pin for the RF-PLL charge pump. Power saving mode control for the RF-PLL section. This pin must be set at ”L” Power-ON. (Open is prohibited.) PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode Power supply voltage input pin for the RF-PLL section(except for the charge pump circuit). Ground for the RF-PLL section. Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RF-PLL. Connction to an external VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. TSSOP 1 2 3 4 5 6 BCC 19 20 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 5 6 7 8 9 10.


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