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MB15F72UL Dataheets PDF



Part Number MB15F72UL
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description Dual Serial Input PLL Frequency Synthesizer
Datasheet MB15F72UL DatasheetMB15F72UL Datasheet (PDF)

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS04-21367-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F72UL s DESCRIPTION The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is.

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www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS04-21367-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F72UL s DESCRIPTION The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a 350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 2.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data. The data format is the same as the previous one MB15F02SL, MB12F72SP . Fast locking is achieved for adopting the new circuit. The new package (BCC20) decreases a mount area of MB15F72UL more than 30% comparing with the former BCC16 (for dual PLL) . MB15F72UL is ideally suited for wireless mobile communications, such as CDMA. s FEATURES • High frequency operation : RF synthesizer : 1300 MHz Max. : IF synthesizer : 350 MHz Max. • Low power supply voltage : VCC = 2.4 to 3.6 V • Ultra low power supply current : ICC = 2.5 mA Typ. (VCC = Vp = 2.7 V, SWIF = SWRF = 0, Ta = +25 °C, in IF, RF locking state) (Continued) s PACKAGES 20-pin plastic TSSOP 20-pad plastic BCC (FPT-20P-M06) (LCC-20P-M05) www.DataSheet4U.com MB15F72UL (Continued) • Direct power saving function : Power supply current in power saving mode Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25 °C) Max. 10 µA (VCC = Vp = 2.7 V) • Software selectable charge pump current : 1.5 mA/6.0 mA Typ. • Dual modulus prescaler : 1300 MHz prescaler (64/65 or 128/129 ) /350 MHz prescaler (8/9 or 16/17) • 23 bit shift resister • Serial input 14-bit programmable reference divider : R = 3 to 16,383 • Serial input programmable divider consisting of : - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 • On−chip phase control for phase comparator • On−chip phase comparator for fast lock and low noise • Built-in digital locking detector circuit to detect PLL locking and unlocking. • Operating temperature : Ta = −40 °C to +85 °C • Serial data format compatible with MB15F02SL • Small package BCC20 (3.4 mm × 3.6 mm × 0.6 mm) s PIN ASSIGNMENTS (TSSOP-20) TOP VIEW (BCC-20) TOP VIEW OSCIN Data Clock GND finIF XfinIF GNDIF VCCIF PSIF VpIF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 LE finRF XfinRF GNDRF VCCRF PSRF OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DoIF LD/fout 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Clock Data LE finRF XfinRF GNDRF VCCRF PSRF VpRF DoRF DoIF DoRF LD/fout VpRF (FPT-20P-M06) (LCC-20P-M05) 2 www.DataSheet4U.com MB15F72UL s PIN DESCRIPTION Pin no. TSSOP BCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name I/O OSCIN GND finIF XfinIF GNDIF VCCIF PSIF VpIF DOIF LD/fout DORF VpRF PSRF VCCRF GNDRF XfinRF finRF LE I Descriptions The programmable reference divider input. TCXO should be connected with an AC coupling capacitor. Prescaler input pin for the IF-PLL. Connection to an external VCO should be via AC coupling. Prescaler complimentary input pin for the IF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the IF-PLL section (except for the charge pump circuit) , the OSC input buffer and the shift register circuit. Power saving mode control for the IF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode Charge pump output pin for the IF-PLL section. Lock detect signal output (LD) /phase comparator monitoring output (fout) pins.The output signal is selected by LDS bit in the serial data. LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal Charge pump output pin for the RF-PLL section. Power saving mode control pin for the RF-PLL section. This pin must be set at “L” when the power supply is started up. (Open is prohibited.) PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode Power supply voltage input pin for the RF-PLL section (except for the charge pump circuit) Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. Load enable signal input pin (with the schmitt trigger circuit) When LE is set “H”, data in the shift register is transferred to the corresponding latch according to the control bit in the serial data. Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in the serial data. Clock input pin for the 23-bit shift register (with the schmitt trigger circuit) One bit of data is shifted into the shift register on.


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