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SPT7862 Dataheets PDF



Part Number SPT7862
Manufacturers SPT
Logo SPT
Description DUAL-CHANNEL A/D CONVERTER
Datasheet SPT7862 DatasheetSPT7862 Datasheet (PDF)

www.DataSheet4U.com SPT7862 10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER FEATURES • Dual-channel, 10-Bit, 40 MSPS analog-to-digital converter • Low power dissipation: 320 mW (typical) • Internal track-and-hold • Single +5 volt supply • Tri-state, TTL/CMOS-compatible outputs • Selectable +3 or +5 V logic I/O • High ESD protection of 3,500 volts minimum APPLICATIONS • • • • • • • • • Video set-top boxes Cellular base stations QPSK/QAM RF demodulation S-video digitizers Composite video digitizers .

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www.DataSheet4U.com SPT7862 10-BIT, 40 MSPS, DUAL-CHANNEL A/D CONVERTER FEATURES • Dual-channel, 10-Bit, 40 MSPS analog-to-digital converter • Low power dissipation: 320 mW (typical) • Internal track-and-hold • Single +5 volt supply • Tri-state, TTL/CMOS-compatible outputs • Selectable +3 or +5 V logic I/O • High ESD protection of 3,500 volts minimum APPLICATIONS • • • • • • • • • Video set-top boxes Cellular base stations QPSK/QAM RF demodulation S-video digitizers Composite video digitizers Portable and handheld instrumentation Medical ultrasound Cable modems Video frame grabbers GENERAL DESCRIPTION The SPT7862 contains two separate 10-bit CMOS analogto-digital converters that have sampling rates of up to 40 MSPS. Each device has its own separate clock and reference inputs so that they can be used independently in multichannel applications or can be driven from the same inputs for demanding quadrature demodulation and S-video applications. On-chip track-and-hold and advanced proprietary circuit design in a CMOS process technology provide very good dynamic performance. The SPT7862 operates from a single +5 V supply. Digital data outputs are user selectable at +3 or +5 V. Output data format is straight binary. The SPT7862 is available in a 64-lead TQFP package (10 x 10 mm) over the industrial temperature range of –40 °C to +85 °C. BLOCK DIAGRAM AVDD AGND DVDD DGND OVDDA (+3.3/5.0 V) VINA VINRA VRHFA VRHSA VRLFA VRLSA CLK A ADC Output Buffers DA9–0 OGNDA Reference Ladder DAVA EN Timing Generation OVDDB (+3.3/5.0 V) Output Buffers VINB VINRB VRHFB VRHSB VRLFB VRLSB CLK B ADC DB9–0 OGNDB Reference Ladder DAVB Timing Generation Signal Processing Technologies, Inc. 4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: [email protected] DataSheet 4 U .com www.DataSheet4U.com ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages AVDD ......................................................................... +6 V DVDD ......................................................................... +6 V Input Voltages Analog Input ................................. –0.5 V to AVDD +0.5 V VREF ................................................................. 0 to AVDD CLK Input ................................................................... VDD AVDD – DVDD ...................................................... ±100 mV AGND – DGND .................................................. ±100 mV Note: Output Digital Outputs ....................................................... 10 mA Temperature Operating Temperature ............................. –40 to +85 °C Junction Temperature ......................................... +175 °C Lead Temperature, (soldering 10 seconds) ........ +300 °C Storage Temperature ............................... –65 to +150 °C 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. PARAMETERS Resolution DC Accuracy Integral Nonlinearity Differential Nonlinearity Analog Input Input Voltage Range Input Resistance Input Capacitance Input Bandwidth Offset Gain Error Reference Input Resistance Voltage Range VRLS VRHS VRHS – VRLS ∆(VRHF – VRHS) ∆(VRLS – VRLF) Conversion Characteristics Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits ƒIN = 3.58 MHz ƒIN = 10.0 MHz Signal-to-Noise Ratio (without Harmonics) ƒIN = 3.58 MHz ƒIN = 10.0 MHz ƒIN = 10.0 MHz V V IV V V V V V V IV IV V V V VI IV IV V V 0 3.0 1.0 VRLS 29 5.0 250 ±2.0 ±2.0 500 – – 4.0 90 75 2.0 AVDD 5.0 TEST CONDITIONS TEST LEVEL MIN 10 ±1.0 ±0.5 VRHS SPT7862 TYP MAX UNITS Bits LSB LSB V kΩ pF MHz LSB LSB Ω V V V mV mV MHz MHz 12 4.0 7 Clock Cycles (Small Signal) 40 2 ns ps(rms) V VI 7.8 9.1 8.3 Bits Bits TA = +25 °C TA = TMIN to TMAX V I IV 52 47 57.9 54.2 dB dB dB SPT DataSheet 4 U .com SPT7862 2 2/23/00 www.DataSheet4U.com ELECTRICAL SPECIFICATIONS TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified. TEST CONDITIONS 9 Distortion bins from 1024 pt FFT TA = +25 °C TA = TMIN to TMAX TEST LEVEL SPT7862 TYP PARAMETERS Dynamic Performance Harmonic Distortion ƒIN = 3.58 MHz ƒIN = 10.0 MHz ƒIN = 10.0 MHz Signal-to-Noise and Distortion (SINAD) ƒIN = 3.58 MHz ƒIN = 10.0 MHz ƒIN = 10.0 MHz Spurious Free Dynamic Range ƒIN = 10.0 MHz Differential Phase Differential Gain Channel-to-Channel Crosstalk ƒIN = 3.58 MHz ƒIN = 10.0 MHz Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Input Capacitance Digital Outputs Logic 1 Voltage Logic 0 Voltage tRISE tFALL Output Enable to Data.


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