STW51000

www.DataSheet4U.com GreenSIDE STW51000 SUPER INTEGRATED DSP ENGINE DATA BRIEF 1 ■ Product Features Figure 1. Package ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 ■ ■ Super Integrated SoC including 2 x ST140 quad MAC DSP engines running at 600MHz and 1 x ARM926 Micro Controller running at 300MHz Double Quad-MAC units Double Quad-ALU (32 and 40-bit) PBGA/HSP-569 4800 MMacs/s - 29000 Mops - 7500 Mips Convolutional Decoder Engine: Table 1. Order Codes – 256 x 12.2 kpbs AMR voice users Part Number Package – Programmable Code Parameters to support STW51000AT PBGA/HSP-569 multi-standards (W-CDMA, TD-SCDMA, CDMA2000 and EDGE) Turbo Decoder Engine: ■ Conditional Instructions to reduce code size and overhead – 28 x 384 kbps (8 iterations) ■ Built-in Coprocessor Interfaces for highly – Programmable Code Parameters to support optimized Instruction Definition multi-standards (W-CDMA, TD-SCDMA and CDMA2000) ■ Compiler Friendly Instruction Set for high performance critical DSP Routines directly from – Includes CRC Processing C – Hardware Interleaver with multi-standard DataSheet4U.com DataShee ■ 8, 16, 32 and 40-bit Data Support support ■ Circular and bit-reversed Data addressing Two 32-channel DMA Engines modes 16Mbit Central Memory shared among DSPs, ■ 32x16 bit Multiplier eases floating point to fixed µC and DMA Engines point conversion One 32-bit External Memory Controller ■ 8-bit Overflow protection One external Master Interface ■ Bit Manipulation One 32-bit Communication Interfac...