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TC74ACT175F Dataheets PDF



Part Number TC74ACT175F
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description Quad D-Type Flip-Flop
Datasheet TC74ACT175F DatasheetTC74ACT175F Datasheet (PDF)

TC74ACT175P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT175P, TC74ACT175F Quad D-Type Flip Flop with Clear The TC74ACT175 is an advanced high speed CMOS QUAD D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. .

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TC74ACT175P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT175P, TC74ACT175F Quad D-Type Flip Flop with Clear The TC74ACT175 is an advanced high speed CMOS QUAD D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. These four flip-flops are controlled by a clock input (CK) and a clear input ( CLR ). The information data applied to the D inputs (D1 thru D4) are transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the positive-going edge of the clock pulse. Reset function is accomplished when the clear input is taken low, and all Q outputs are kept in low level regardless of other input conditions. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: fmax = 160 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 8 μA (max) at Ta = 25°C Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. Balanced propagation delays: tpLH ∼− tpHL Pin and function compatible with 74F175 Pin Assignment TC74ACT175P TC74ACT175F Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Start of commercial production 1989-11 1 2014-03-01 IEC Logic Symbol TC74ACT175P/F Truth Table Inputs CLR D CK L X X H L H H H X X: Don’t care Outputs QQ L H L H H L Qn Qn Function Clear ⎯ ⎯ No Change System Diagram 2 2014-03-01 TC74ACT175P/F Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature VCC VIN VOUT IIK IOK IOUT ICC PD Tstg −0.5 to 7.0 V −0.5 to VCC + 0.5 V −0.5 to VCC + 0.5 V ±20 mA ±50 mA ±50 mA ±200 mA 500 (DIP) (Note 2)/180 (SOP) mW −65 to 150 °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time VCC VIN VOUT Topr dt/dV 4.5 to 5.5 0 to VCC 0 to VCC −40 to 85 0 to 10 V V V °C ns/V Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 3 2014-03-01 TC74ACT175P/F Electrical Characteristics DC Characteristics Characteristics High-level input voltage Low-level input voltage High-level output voltage Symbol VIH VIL VOH Low-level output voltage VOL Input leakage current IIN ICC Quiescent supply current IC Test Condition ⎯ Ta = 25°C Ta = −40 to 85°C Unit VCC (V) Min Typ. Max Min Max 4.5 to 5.5 2.0 ⎯ ⎯ 2.0 ⎯ V ⎯ 4.5 to 5.5 ⎯ ⎯ 0.8 ⎯ 0.8 V VIN IOH = −50 μA 4.5 = VIH or IOH = −24 mA 4.5 VIL IOH = −75 mA (Note) 5.5 VIN IOL = 50 μA 4.5 = VIH or IOL = 24 mA 4.5 VIL IOL = 75 mA (Note) 5.5 4.4 4.5 ⎯ 4.4 ⎯ 3.94 ⎯ ⎯ 3.80 ⎯ V ⎯ ⎯ ⎯ 3.85 ⎯ ⎯ 0.0 0.1 ⎯ 0.1 ⎯ ⎯ 0.36 ⎯ 0.44 V ⎯ ⎯ ⎯ ⎯ 1.65 VIN = VCC or GND 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA VIN = VCC or GND Per input: VIN = 3.4 V Other input: VCC or GND 5.5 ⎯ ⎯ 8.0 ⎯ 80.0 μA 5.5 ⎯ ⎯ 1.35 ⎯ 1.5 mA Note: This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Test Condition Minimum pulse width tW (L) ⎯ (CK) tW (H) Minimum pulse width tW (L) ⎯ ( CLR ) Minimum set-up time ts ⎯ Minimum hold time th ⎯ Minimum removal time trem ⎯ ( CLR ) Ta = Ta = −40 to 25°C 85°C Unit VCC (V) Limit Limit 5.0 ±.


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