IBM25PPC405GP

www.DataSheet4U.com PowerPC 405GP Embedded Processor Data Sheet Features IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications 4KB on-chip memory (OCM) External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Synchronous or asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts Programmable timers Two serial ports (16550 compatible UART) One IIC interface General purpose I/O (GPIO) available Supports JTAG for board level testing DMA support for external peripherals, internal UART and memory Internal processor local Bus (PLB) runs at DataSheet4U.com SDRAM interface frequency - Scatter-gather chaining supported - Four channels Supports PowerPC processor boot from PCI memory e DataShe Description Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, low-power solution that interfaces to a wide range of pe...