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RD38F4460LVY Dataheets PDF



Part Number RD38F4460LVY
Manufacturers Intel
Logo Intel
Description Wireless Memory System
Datasheet RD38F4460LVY DatasheetRD38F4460LVY Datasheet (PDF)

www.DataSheet4U.com Intel StrataFlash Wireless Memory System (LV18 SCSP) 1024-Mbit LVX Family with LPSDRAM Datasheet Product Features ■ ■ ■ ■ ■ ■ Device Memory Architecture ■ — Flash die density: 128-, 256-Mbit — LPSDRAM die density: 128-, 256-Mbit — Top or Bottom parameter flash configuration Device Voltage ■ — Core: VCC = 1.8 V (typ.) — I/O: VCCQ = 1.8 V (typ.) Device Common Performance ■ — Buffered EFP: 5µs / Byte (typ.) per die — Buffer Program: 7µs / Byte (typ.) per die — Concurre.

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www.DataSheet4U.com Intel StrataFlash Wireless Memory System (LV18 SCSP) 1024-Mbit LVX Family with LPSDRAM Datasheet Product Features ■ ■ ■ ■ ■ ■ Device Memory Architecture ■ — Flash die density: 128-, 256-Mbit — LPSDRAM die density: 128-, 256-Mbit — Top or Bottom parameter flash configuration Device Voltage ■ — Core: VCC = 1.8 V (typ.) — I/O: VCCQ = 1.8 V (typ.) Device Common Performance ■ — Buffered EFP: 5µs / Byte (typ.) per die — Buffer Program: 7µs / Byte (typ.) per die — Concurrent Buffered EFP: 6.4-Mbps effective with 4 flash dies Device Common Architecture DataSheet4U.com ■ — Asymmetrical blocking structure — 16-KWord parameter blocks (Top or Bottom); 64-KWord main blocks ■ — Zero-latency block locking — Absolute write protection with block lock down using F-VPP and F-WP# Device Packaging — 103 active balls; 9 x 12 ball matrix ■ — Area: 9 x 11 mm to 11 x 11 mm — Height: 1.4 mm SDRAM Architecture and Performance — Clock rate: 105 MHz — Four internal banks — Burst Length: 1, 2, 4, 8, or full page Code Segment Flash Read Performance — 85 ns initial access — 25 ns Asynchronous Page read — 14 ns Synchronous read (tCHQV) — 54 MHz (max.) CLK Data Segment Flash Performance — 170 ns initial access — 55 ns Asynchronous Page read Code Segment Flash Architecture — Hardware Read-While-Write/Erase — Multiple 8-Mbit / 16-Mbit partition sizes — 2-Kbit One-Time-Programmable Protection Register Data Segment Flash Architecture — Software Read-While-Write/Erase — Single partition size die Flash Software — Intel FDI, Intel PSM, and Intel VFM — Common Flash Interface — Basic/Extended Command Set Quality and Reliability — Extended temperature: –25 °C to +85 °C — Minimum 100 K flash block erase cycle — 0.13 µm ETOX VIII flash technology DataShee Intel StrataFlash® Wireless Memory System (LV18 SCSP) with Low-Power SDRAM (LVX family) offers a variety of high performance code segment, large embedded data segment, and low-power SDRAM combinations in a common package on 0.13 µm ETOX™ VIII flash technology. The LVX family integrates up to two code segment flash dies, two data segment flash dies, and two low-power SDRAM dies or one SRAM die in a common x16D Performance ballout. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 300945-006 October 2004 DataSheet4U.com DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com et4U.com DataShee DataSheet4U.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS IN.


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