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MN101D10F , MN101D10G
Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time Interrupts
With main clock operated When sub-clock operated MN101D10F 96 K 2.5 K QFP100-P-1818B
*Lead-free
MN101D10G 128 K 3.5 K
0.1397 µ s (at 4.0 V to 5.5 V, 14.32 MHz) 71.5 µ s (at 2.7 V to 5.5 V fixed to 14.32 MHz internal frequency division) 61 µ s (at 2.5 V to 5.5 V, 32.768 kHz)
• RESET • Runaway • External 0 • External 1 • External 2 • External 3 • External 4 • Timer 0 • Timer 1 • Timer 2 • Timer 3 • Timer 6 • Capstan FG • Control • HSW • Cylinder(Drum) FG • Servo V-sync • Synchronous output • OSD • XDS • Serial 0 • Serial 1 • Serial 2 • PWM 4 • OSDV-sync Timer counter 0: 8-bit × 1 (timer function) Clock source ····················· 1/4, 1/16 of system clock frequency Interrupt source ················· overflow of timer counter 0 Timer counter 1: 8-bit × 1 (timer function, linear timer counter function) Clock source ····················· 1/4 of system clock frequency; CTL signal Interrupt source ················· overflow of timer counter 1 Timer counter 2: 16-bit × 1 (timer function, input capture,duty judgment of CTL signal(VISS/VASS detection function), generation of remote control output carrier frequency) Clock source ····················· 1/4, 1/16, 1/24 of system clock frequency Interrupt source ················· overflow of timer counter 2; input of CTL specified edge; underflow of timer 2 shift register 4-bit counter; coincidence of timer 2 shift register with timer 2 shift register compare register Timer counter 3: 16-bit × 1 (timer function, generation of serial transmission clock) Clock source ····················· 1/4, 1/16 of system clock frequency Interrupt source ················· overflow of timer counter 3 Timer counter 5: 19-bit × 1 (watchdog, stable oscillation waiting function) Clock source ····················· system clock Watchdog interrupt source ··· 1/2 16, 1/219 of timer counter 5 frequency Clear by stable oscillation ··· after 256 counts by timer counter 5 (2 18 counts of OSC oscillation clock) Timer counter 6: 16-bit × 1 (clock function [max. 2 s]) Clock source ····················· 1/512 of OSC oscillation clock frequency; XI oscillation clock; 1/8, 1/128 of system clock frequency Interrupt source ················· 1/213, 1/2 14, 1/215 overflow of timer counter 6 Serial 0: 8-bit × 1 (synchronous type) (transfer direction of MSB/LSB selectable, start condition function) Clock source ····················· 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency; NSBT0 pin input Serial 1: 8-bit × 1 (synchronous type/remote control transmission) (transfer direction of MSB/LSB selectable, start condition function) Clock source ····················· 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 of system clock frequency; 2-division timer 3 output; NSBT1 pin input Remote control clock ······· 2-division timer 3 output Serial 2: 8-bit × 1 (I 2C) (master transmission/reception, slave transmission/reception) Clock source ····················· 1/144 to 1/252 of system clock; SCK pin input
Timer Counter
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Serial Interface
MAD00043BEM
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MN101D10F, MN101D10G
OSD
Display mode Applicable broadcasting system Screen configuration Character type Character size Enlarged characters Character interpolation Line background color Line background intensity Screen background color : Character color Character intensity Border function Border brightness Blinking Inverted character Halftone Input Clamp method Output Measure against image fluctuation Dot clock MESECAM compatibility
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menu(intermal synchronized) display, superimpose(externally synchronized) display NTSC, PAL, PAL-M, PAL-N 24 characters × 2n rows (n = 1 to 6) max. 256 character types (variable, include special characters) 12 × 18 dots (vertical direction: 1 dot for 2H at not enlargement) each × 2 settings in horizontal and vertical none 8-hue settable in the row unit at menu display 8 gradations settable in the row unit 8-huesettable at menu display white 8 gradations settable in the row unit 1-dot border in 8 directions 4 gradations settable in the row unit none (covered by software) settable in the character unit none composite video signal input (output level: 1 V[p-p] / 2 V[p-p]) sync tip clamp, clamp level in 4 levels composite video output built-in AFC circuit 1/2 of OSC oscillation clock (automatic phase adjustment) Subcarrier leak function for superimpose display
XDS ROM Correction I/O Pins A/D Inputs PWM ICR OCR Special Ports Notes I/O Input
Built-in U.S. closed caption data slicer (optional 1 line data can be extracted.)
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Correcting address designation: up to 3 addresses possible Correction method: correction program being saved in internal RAM 76 1 • Common use: 56 • Common use: 1 8-bit × 12-ch. (without S/H) 13-bit × 2-ch. (at repetitio.