ICS527-02

www.DataSheet4U.com ICS527-02 Clock Slicer User Configurable PECL Input Zero Delay Buffer Description The ICS527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates when the rising clock edges are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-02 aligns rising edges on PECLIN with FBIN at a ratio determined by the reference and feedback dividers. For a PECL input and output clock with zero delay, use the ICS527-04. For a CMOS input and PECL output with zero delay, use the ICS527-03. Features Packaged as 28-pin SSOP (150 mil body) Synchronizes fractional clocks rising edges PECL IN to CMOS OUT Pin selectable dividers Zero input to output skew User determines the output frequency—no software needed Slices frequency or period Input clock frequency of 1.5 MHz to 200 MHz Output clock frequencies from 2.5 MHz to 160 MHz Very low jitter Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low-power CMOS process Industrial temperature version available Block Diagram R6:R0 7 PECLIN PECLIN Reference Divider Phase Comparator, Charge Pump, and Loop Filter FBIN Feedb...