MC100EP195

3.3 V ECL Programmable Delay Chip MC100EP195 The MC100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and www.onsemi.com multiplexers as shown in the logic diagram, Figure 3. The delay increment of the EP195 has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of 1 32 real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent LQFP−32 FA SUFFIX QFN32 MN SUFFIX changes in D[10:0]. The approximate delay values for varying tap CASE 561AB CASE 488AM numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 4. Because the EP195 is designed using a chain of multiplexers it has a MARKING DIAGRAMS* fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched by LEN, in cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Switching devices from all “1” states on D[0:9] with SETMAX LOW MC100 EP195 AWLYYWWG 1 MC100 EP195 AWLYYWWG to all “0” states on D[0:9] with SE...