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MB84VD2208xEA Dataheets PDF



Part Number MB84VD2208xEA
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description (MB84VD2208xEA / MB84VD2209xEA) 32M (X 8/X16) FLASH MEMORY & 2M (X 8/X16) STATIC RAM
Datasheet MB84VD2208xEA DatasheetMB84VD2208xEA Datasheet (PDF)

( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50205-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 32M (× 8/×16) FLASH MEMORY & 2M (× 8/×16) STATIC RAM MB84VD2208XEA-90/MB84VD2209XEA-90 s FEATURES • Power supply voltage of 2.7 to 3.3V • High performance 90 ns maximum access time (Flash) 85 ns maximum access time (SRAM) • Operating Temperature –25 to +85°C • Package 73-ball FBGA (Continued) s PRODUCT LINE UP Flash Memory Ordering Part No. VCCf, VCCs.

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( DataSheet : www.DataSheet4U.com ) FUJITSU SEMICONDUCTOR DATA SHEET DS05-50205-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 32M (× 8/×16) FLASH MEMORY & 2M (× 8/×16) STATIC RAM MB84VD2208XEA-90/MB84VD2209XEA-90 s FEATURES • Power supply voltage of 2.7 to 3.3V • High performance 90 ns maximum access time (Flash) 85 ns maximum access time (SRAM) • Operating Temperature –25 to +85°C • Package 73-ball FBGA (Continued) s PRODUCT LINE UP Flash Memory Ordering Part No. VCCf, VCCs = 3.0 V +0.3 V –0.3 V SRAM MB84VD2208XEA-90/MB84VD2209XEA-90 90 90 40 85 85 45 Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns) s PACKAGE 73-ball plastic FBGA ( BGA-73P-M01) www.DataSheet4U.com www.DataSheet4U.com MB84VD2208XEA-90/MB84VD2209XEA-90 (Continued) 1. FLASH MEMORY • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Minimum 100,000 write/erase cycles • Sector erase architecture Eight 4 K words and sixty three 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD2208XEA: Top sector MB84VD2209XEA: Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCCf write inhibit ≤ 2.5 V • Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2208XEA:SA69,SA70 MB84VD2209XEA:SA0,SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduse by 40%. • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to “MBM29DL32XTE/BE” data sheet in detailed function 2. SRAM • Power dissipation Operating : 40 mA max. Standby : 7 µA max. • Power down features using CE1s and CE2s • Data retention supply voltage: 1.5 V to 3.3 V • CE1s and CE2s Chip Select • Byte data control: LBs (DQ0 to DQ7), UBs(DQ8 to DQ15) Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84VD2208XEA-90/MB84VD2209XEA-90 s PIN ASSIGNMENT (Top View) 10 N.C. N.C. N.C. N.C. N.C. N.C. 9 A15 N.C. N.C. A16 CIOf VSS 8 A11 .


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