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MK3805 Dataheets PDF



Part Number MK3805
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Buffer/Clock Driver
Datasheet MK3805 DatasheetMK3805 Datasheet (PDF)

P R E L I M I N A RY I N F O R M AT I O N MK3805 Buffer/Clock Driver Description The MK3805 is a non-inverting clock driver/buffer providing two independent banks of four outputs each. These buffers have a tri-state output enable input (active low) with 1-input, 5-output configuration per group. The skew between the outputs of the same package is 0.5 ns and the skew between the outputs of different packages is 0.8 ns. The maximum input to output delay is 4.5 ns. Features • • • • • • • • Packa.

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P R E L I M I N A RY I N F O R M AT I O N MK3805 Buffer/Clock Driver Description The MK3805 is a non-inverting clock driver/buffer providing two independent banks of four outputs each. These buffers have a tri-state output enable input (active low) with 1-input, 5-output configuration per group. The skew between the outputs of the same package is 0.5 ns and the skew between the outputs of different packages is 0.8 ns. The maximum input to output delay is 4.5 ns. Features • • • • • • • • Packaged in 20 pin SSOP or 20 pin SOIC Five outputs for each bank with one clock input Two separate banks of five outputs each Advanced, low power, CMOS process Ten output clocks Two separate inputs Industrial temperature range -40°C to +85°C Hysteresis on all inputs Block Diagram VDD 2 OEA INA OA0-4 5 OEB INB 5 OB0-4 MON 3 GND www.DataSheet4U.com MDS 3805 A 1 Revision 072203 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com www.DataSheet4U.com Preliminary Information MK3805 Buffer/Clock Driver Pin Assignment VCC OA0 OA1 OA2 GND OA3 OA4 GND OEA INA 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OB0 OB1 OB2 GND OB3 OB4 MON OEB INB Truth Table Inputs OEA, OEB L L H H INA, INB L H L H L H Z Z Outputs OAN, OBN MON L H L H 20 pin (150 mil) SSOP/20 pin (300mil) SOIC Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name VCC OA0 OA1 OA2 GND OA3 OA4 GND OEA INA INB OEB MON OB4 OB3 GND OB2 OB1 OB0 VCC Pin Type Power Output Output Output Power Output Output Power Input Input Input Input Output Output Output Power Output Output Output Power Connect to +3.3 V Clock output. Clock output. Clock output. Connect to ground. Clock output. Clock output. Connect to ground. Pin Description Tri state output enable input (active low). Clock input. Clock input. Tri state output enable input (active low). Monitor output. Clock output. Clock output. Connect to ground. Clock output. Clock output. Clock output. Connect to +3.3 V MDS 3805 A 2 Revision 072203 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com Preliminary Information MK3805 Buffer/Clock Driver External Components The MK3805 requires a minimum number of external components for proper operation. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through the signal layers. Other signal traces should be routed away from the MK3805. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Decoupling Capacitors Decoupling capacitors of 0.01µF must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK3805. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5V to VDD+0.5V -40 to +85°C -65 to +150°C 175°C 260°C MDS 3805 A 3 Revision 072203 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com Preliminary Information MK3805 Buffer/Clock Driver Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. -40 +3.13 Typ. +3.3 Max. +85 +3.46 Units °C V DC Electrical Characteristics .


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