MT48LC4M32LFFC

128Mb: x16, x32 MOBILE SDRAM SYNCHRONOUS DRAM Features Temperature Compensated Self Refresh (TCSR) Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT auto precharge, and Auto Refresh Modes Self Refresh Mode; standard and low power 64ms, 4,096-cycle refresh LVTTL-compatible inputs and outputs Low voltage power supply Partial Array Self Refresh power-saving mode OPTIONS MARKING LC G V MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF, MT48LC8M16LFF4, MT48V8M16LFF4, MT48V8M16LFFF MT48LC4M32LFFC, MT48LC4M32LFF5, MT48V4M32LFFC, MT48V4M32LFF5 For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds Figure 1: Pin Assignment (Top View) 54-Ball FBGA 1 A B C D E F G H J VSS 2 DQ15 3 VSSQ 4 5 DQ14 DQ13 VDDQ DQ12 DQ11 DQ10 DQ9 UDQM VDD/VDDQ 3.3V/3.3V 3.0V/3.0V1 2.5V/2.5V – 1.8V Configurations 8 Meg x 16 (2 Meg x 16 x 4 banks) 4 Meg x 32 (1 Meg x 32 x 4 banks) Package/Ball out 54-ball FBGA (8mm x 9mm)2 54-ball FBGA (8mm x 9mm)2 Lead-Free 54-ball VFBGA (8mm x 8mm)2 54-ball VFBGA (8mm x 8mm)2 Lead-Free 90-ball FBGA (11mm x 13mm)3 90-ball FBGA (11mm x 13mm)3 Lead-Free 90-ball VFBGA (8mm x 13mm)3 90-ball VFBGA (8mm x 13mm)3 Lead-Free Timing (Cycle Time) 8ns @ CL = 3 (125 MHz) 10ns @ CL = 3 ...