Document
DATA SHEET
512M bits DDR2 SDRAM
EDE5104AESK (128M words × 4 bits) EDE5108AESK (64M words × 8 bits)
Description
The EDE5104AESK is a 512M bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDE5108AESK is a 512M bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 4 banks. They are packaged in 60-ball FBGA (µBGA) package.
Features
• Power supply: VDD, VDDQ = 1.8V ± 0.1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data mask (DM) for write data • Burst lengths: 4, 8 • /CAS Latency (CL): 3, 4, 5 • Auto precharge operation for each burst access • Auto refresh and self refresh modes • Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • SSTL_18 compatible I/O • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation. • FBGA (µBGA) package with lead free solder (Sn-Ag-Cu)
Document No. E0562E50 (Ver. 5.0) Date Published May 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2004-2005
EDE5104AESK, EDE5108AESK
Ordering Information
Part number EDE5104AESK-6E-E EDE5104AESK-5C-E EDE5104AESK-4A-E EDE5108AESK-6E-E EDE5108AESK-5C-E EDE5108AESK-4A-E Mask version E Organization (words × bits) 128M × 4 Internal Banks 4 Speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) Package 60-ball FBGA (µBGA)
64M × 8
Part Number
E D E 51 04 A E SK - 6E - E
Elpida Memory
Type D: Monolithic Device
Product Family E: DDR2
Environment code E: Lead Free
Density / Bank 51: 512Mb /4-bank Organization 04: x4 08: x8 Power Supply, Interface A: 1.8V, SSTL_18
Speed 6E: DDR2-667 (5-5-5) 5C: DDR2-533 (4-4-4) 4A: DDR2-400 (3-3-3) Package SK: FBGA (µBGA with back cover) Die Rev.
Data Sheet E0562E50 (Ver. 5.0)
2
EDE5104AESK, EDE5108AESK
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA (µBGA)
1
A
2
3
7
8
9
VDD NU/ /RDQS VSS
B C D
(NC)*
(NC)*
VSSQ /DQS VDDQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
(Top view)
DQ6 DM/RDQS (NC)* VSSQ (DM)*
VDDQ
DQ4
DQ1 VDDQ
VSSQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
(NC)*
DQ7
VDDQ
(NC)*
DQ5
E
VDDL VREF
F
VDD
ODT
CKE
G
NC
H
BA0
A10
VDD
J
VSS
K L
A3
A7
VSS
VDD
A12
Note: ( )* mark.