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STA505
40V 3.5A QUAD POWER HALF BRIDGE
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MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION
MULTIPOWER BCD TECHNOLOGY
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PowerSO36
ORDERING NUMBER: STA505
DESCRIPTION STA505 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particularly designed to make the outAUDIO APPLICATION CIRCUIT (Dual BTL)
IN1A IN1A +3.3V IBIAS CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR PWRDN FAULT
29 23 24
TRI-STATE
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C58 100nF
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IN1B C53 100nF C60 100nF IN2A IN2B
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TH_WAR IN1B VDD VDD VSS VSS VCCSIGN VCCSIGN IN2A GND-Reg IN2B GNDSUB
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25 27 26 28 30 21 22 33 34 35 36 31 20 19
PROTECTIONS & LOGIC
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15 17 16 14 12 11 10 13 7
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VCC1A C30 1µF OUT1A OUT1A GND1A VCC1B C31 1µF OUT1B OUT1B
put stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 50 + 50W @ THD = 10% at Vcc 30V output power on 8Ω load and 80W @ THD = 10% at Vcc 36V on 8Ω load in single BTL configuration. The input pins have threshold proportional to Ibias pin voltage.
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C52 330pF R63 20
U 4
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+VCC C55 1000µF
L18 22µH C20 100nF R98 6 C99 100nF C23 470nF C101 100nF
M2
M5
R100 6 C21 100nF
L19 22µH
M4
GND1B
REGULATORS
VCC2A C32 1µF OUT2A OUT2A
M17 8 9 M15
L113 22µH C110 100nF C109 330pF R103 6 R104 20
6
GND2A
4 M16
VCC2B C33 1µF OUT2B OUT2B
GND-Clean
R102 6 C111 100nF
3 2
C107 100nF C108 470nF C106 100nF
32 M14
L112 22µH
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5
GND2B
D00AU1148B
July 2003
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PIN FUNCTION
N° 1 35 ; 36 15 12 7 4 14 13 6 5 16 ; 17 10 ; 11 8;9 2;3 29 30 31 32 21 ; 22 33 ; 34 25 26 27 24 28 19 23 18 20 Pin GND-SUB Vcc Sign Vcc1A Vcc1B Vcc2A Vcc2B GND1A GND1B GND2A GND2B OUT1A OUT1B OUT2A OUT2B IN1A IN1B IN2A IN2B Vdd Vss PWRDN TRI-STATE FAULT CONFIG TH-WAR GND-clean IBIAS NC GND-Reg Substrate ground Signal Positive Supply Positive Supply Positive Supply Positive Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Output half bridge 1A Output half bridge 1B Output half bridge 2A Output half bridge 2B Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5V Regulator referred to ground 5V Regulator referred to +Vcc Stand-by pin Hi-Z pin Fault pin advisor Configuration pin Thermal warning advisor Logical ground High logical state setting voltage Not connected Ground for regulator Vdd Description
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STA505
FUNCTIONAL PIN STATUS
PIN NAME FAULT FAULT (*) TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR(*) CONFIG CONFIG(**) Logical value 0 1 0 1 0 1 0 1 0 1 IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C Normal operation Normal Operation OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)
(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**): To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
PIN CONNECTION
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG IBIAS VDD VDD GND-Reg GND-Clean
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
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ABSOLUTE MAXIMUM RATINGS
Symbol VCE Vmax Top Tstg, Tj Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins 23 to 32 Operating Temperature Range Storage and Junction Temperature Value 40 5.5 0 to 70 -40 to 150 Unit V V °C °C
THERMAL DATA
Symbol Tj-case TjSD Twarn thSD Parameter Thermal Resistance Junction to Case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min. Typ. Max. 2.5 Unit °C/W °C °C °C
ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 30V; T = 25°C unless otherwise specified)
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-H VIN-L IIN-H IIN-L Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON Matching Power Nchannel RdsON Matching Low current Dead Time (static) Id=1A; Vcc=35V Id=1A Id=1A see test circuit no.1; see fig. 1 95 95 10 20 50 100 100 25 25 9 36 Ibias/2 +300mV Ibias/2 -300mV Pin voltage = Ibias Pin voltage = 0.3V 1 1 Test conditions Min. Typ. 200 Max. 270 50 Unit mΩ µA % % ns ns ns ns ns ns V V V µA µA
High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω Id=3.5A; see fig. 3 Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage L.