Document
MC33001/A/B MC34001/A/B MC35001/A/B GENERAL PURPOSE SINGLE JFET OPERATIONAL AMPLIFIERS
. . . . . . . .
LOW POWER CONSUMPTION WIDE COMMON-MODE (UP TO VCC+) AND DIFFERENTIAL VOLTAGE RANGE LOW INPUT BIAS AND OFFSET CURRENT OUTPUT SHORT-CIRCUIT PROTECTION HIGH INPUT IMPEDANCE J–FET INPUT STAGE INTERNAL FREQUENCY COMPENSATION LATCH UP FREE OPERATION HIGH SLEW RATE : 16V/µs (typ)
N DIP8 (Plastic Package)
D SO8 (Plastic Micropackage)
DESCRIPTION These circuits are high speed J–FET input single operational amplifiers incorporating well matched, high voltage J–FET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset current, and low offset voltage temperature coefficient. PIN CONNECTIONS (top view) ORDER CODES
Part Number MC34001/A/B MC33001/A/B MC35001/A/B Temperature
o o 0 C, +70 C o o –40 C, +105 C
Package N • • • D • •
33001-01.TBL
•
–55 C, +125 C
o
o
1
2 -
8 7
6
3
4
+
1 2 3 4 5 6 7 8
-
Offset Null 1 Inverting input Non-inverting input VCCOffset Null 2 Output VCC+ N.C.
5
April 1995
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MC33001/A/B - MC34001/A/B - MC35001/A/B
SCHEMATIC DIAGRAM
V CC
Non-inverting input Inverting input
100 Ω
200 Ω Output
100 Ω 30k
8.2k
1.3k V CC
35k
1.3k
35k
100 Ω
Offset Null1
Offset Null2
INPUT OFFSET VOLTAGE NULL CIRCUITS
MC34001
N1
N2 100k Ω V CC
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI Vid Ptot Toper Supply Voltage - (note 1) Input Voltage - (note 3) Differential Input Voltage - (note 2) Power Dissipation Output Short-circuit Duration (note 4) Operating Free Air Temperature Range MC34001, A, B MC33001, A, B MC35001, A, B Parameter Value ±18 ±15 ±30 680 Infinite
33001-02.TBL
33001-04.EPS
Unit V V V mW
o
0 to 70 –40 to 105 –55 to 125 –65 to 150
C
Tstg
Notes :
Storage Temperature Range
o
C
1. All voltage values, except differential voltage, are with respect to the zero reference level (ground) of the supply voltages where the zero reference level is the midpoint between VCC+ and VCC-. 2. Differential voltages are at the non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 volts, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and /or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
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33001-03.EPS
MC33001/A/B - MC34001/A/B - MC35001/A/B
ELECTRICAL CHARACTERISTICS VCC = ±15V, Tamb = 25oC (unless otherwise specified)
Symbol Parameter Input Offset Voltage (RS ≤ 10kΩ) Tamb = 25oC MC35001B, MC34001B, MC33001B MC35001A, MC34001A, MC33001A Tmin. ≤ Tamb ≤ Tmax. MC35001B, MC34001B, MC33001B MC35001A, MC34001A, MC33001A Input Offset Voltage Drift Input Offset Current * Tamb = 25oC Tmin. ≤ Tamb ≤ Tmax. Input Bias Current * Tamb = 25oC Tmin. ≤ Tamb ≤ Tmax. Large Signal Voltage Gain (RL = 2kΩ, VO = ±10V) Tamb = 25oC Tmin. ≤ Tamb ≤ Tmax. Supply Voltage Rejection Ratio (RS ≤10kΩ) Tamb = 25oC Tmin. ≤ Tamb ≤ Tmax. Supply Current, no Load o Tamb = 25 C Tmin. ≤ Tamb ≤ Tmax. Input Common Mode Voltage Range Common Mode Rejection Ratio (RS ≤ 10kΩ) Tamb = 25oC Tmin. ≤ Tamb ≤ Tmax. Output Short-circuit Current Tamb = 25oC Tmin. ≤ Tamb ≤ Tmax. Output Voltage Swing o Tamb = 25 C Tmin. ≤ Tamb ≤ Tmax. SR tr KOV GBP Ri THD en ∅m RL RL RL RL = = = = 2kΩ 10kΩ 2kΩ 10kΩ ±11 50 25 80 80 MC35001A,B MC33001A,B MC34001A,B Min. Vio Typ. Max. Min. MC35001 MC33001 MC34001 Typ. 3 3 0.4 5 2 13 7 4 10 5 100 4 200 20 25 15 70 70 2.5 2.8 ±11 10 5 100 4 200 20 µV/oC pA nA pA nA V/mV 200 200 dB 86 86 mA 1.4 +15 -12 86 1.4 +15 -12 86 mA 10 10 10 12 10 12 12 40 60 60 10 10 10 12 10 12 12 40 60 60 V 12 13.5 12 13.5 V/µs µs 0.1 10 2.5 4 1012 0.01 15 45 2.5 0.1 % 10 MHz 4 1012 0.01 15 45
33001-03.TBL
Unit
Max. mV 10
DVio Iio
Iib
20
20
Avd
SVR
ICC
2.5 2.8 V dB
Vicm CMR
80 80
70 70
Ios ±VOPP
Slew Rate (Vin = 10V, RL = 2kΩ, CL = 100pF, Tamb = 25oC, unity gain) Rise Time (Vin = 20mV, RL = 2kΩ, CL = 100pF, o Tamb = 25 C, unity gain) Overshoot (Vin = 20mV, RL = 2kΩ, CL = 100pF, Tamb = 25oC, unity gain) Gain Bandwidth Product (f = 100kHz, Tamb = 25oC, Vin = 10mV, RL = 2kΩ, CL = 100pF) Input Resistance Total Harmonic Distortion (f = 1kHz, AV = 20dB, o RL = 2kΩ, CL = 100pF, Tamb = 25 C, VO = 2VPP) Equivalent Input Noise Voltage (f = 1kHz, Rs = 100Ω) Phase Margin
16
16
Ω % nV √ Hz Degrees
* The input bias currents are junction leakage currents which approximately double for every 10oC increase in the junction temperature.
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MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE VERSUS FREQUENCY MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE VERSUS FREQUENCY
30
30
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE (V)
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE (V)
V CC = 25 20 V CC = 15 10 5 0 100 1K V CC =
15V
R L = 2 kΩ T a m b = + 2 5˚ C S ee Figure 2
R L= 10kΩ
25 20 15 10 5 0 100
VCC= VCC=
15V
10V
T a m b = +25˚ C Se e Figure 2
10V
VCC=
5V
5V
1.