MCF5407

Advance Information MCF5407PB/D Rev. 3.3, 2/2003 MCF5407 Integrated ColdFire® Microprocessor Product Brief w w w .D at h S a t e e 4U . m o c This document is an overview of the MCF5407 ColdFire processor, focusing on feature enhancements over the MCF5307. It includes general descriptions of features and of the various modules incorporated in the MCF5407. It describes the V4 programming model as it is implemented in the MCF5407. 1.1 Features The MCF5407 integrated microprocessor combines a Version 4 ColdFire processor core with the following components, as shown in Figure 1: Harvard architecture memory system with 16-Kbyte instruction cache and 8-Kbyte data cache Two, 2-Kbyte on-chip SRAMs Integer/fractional multiply-accumulate (MAC) unit Divide unit System debug interface DRAM controller for synchronous and asynchronous DRAM Four-channel DMA controller Two general-purpose timers Two UARTs, one that supports synchronous operations I2C™ interface Parallel I/O interface System integration module (SIM) w w w .D t a S a e h t e U 4 .c m o Designed for embedded control applications, the MCF5407 delivers 316 Dhrystone MIPS at 220 MHz or 233 Dhrystone MIPS at 162 MHz. w w w .D at h S a t e e 4U . m o c Features V4 COLDFIRE PROCESSOR COMPLEX JTAG Branch Logic 8-Entry Branch Cache IAG IC1 IC2 IED Instruction Fetch Pipeline (IFP) . . . 128-Entry Prediction Table CCR Ten-Instruction FIFO Buffer Operand Execution Pipeline...