Document
m o .c U 4 t e FEATURES e h • Full CMOS output swing with 40-mA output drive S output capability. 25-mA drive at TTL level. a t • Advanced, low power, sub-micron CMOS processes. a • 25MHz .D fundamental crystal or clock input. • 4 outputs at 50MHz, 2 outputs selectable at 25MHz or w 125MHz, 1 output selectable at 25MHz or 100MHz. w SDRAM selectable frequencies of 66.6, 75, 83.3, w• 2 100MHz (Double Drive Strength).
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PLL650-02
Low EMI Network LAN Clock
PIN CONFIGURATION
VDD XIN XOUT/50MHz_OE*^ GND VDD 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 VDD VDD 25MHz/100MHz GND SDRAMx2 GND
All non SDRAM outputs can be disabled (tri-state) Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% for SDRAM and 100MHz output. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 24-Pin 150mil SSOP.
DESCRIPTIONS
The PLL 650-02 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25 MHz crystal, and produces multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs, with double drive strength for its SDRAM outputs.
BLOCK DIAGRAM
XIN XOUT
XTAL OSC
m o .c U 4 t e e h S a t a .D w w w
50MHz/FS0*^ GND 50MHz/FS1*^ 50MHz/FS2*T FS3T 10 11 12 50MHz/SS0*T VDD
Note: SDRAMx2: Double Drive strength. T: Tri-Level input ^: Internal pull-up resistor. *: Bi-directional pin (input value is latched upon power-up).
FREQUENCY TABLE
FS0 0 SDRAM
PLL650-02
SDRAMx2 VDD VDD
25MHz/125MHz GND
25MHz/125MHz
FS1 0
FS3 0
Pin 13, 15 Disable
FS2 0 M 1
Pin 22 25MHz Disable 100MHzSST
100MHzSST
0
1
75MHz SST
M 1
125MHz 25MHz
1 1
0 1
83.3MHzSST 66.6MHzSST
FS(2:3): Tri-level inputs. SST: SST modulation applied (see selection table)
4
50MHz (can be disabled) 25MHz/125MHz (can be disabled)
2
Control Logic
2
SDRAM (66.6, 75, 83.3, 100MHz)
FS (0:3) 1
25MHz/100MHz (can be disabled)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
m o .c 4U t e e h S a t a D . w w w
Rev 05/02/01 Page 1
PLL650-02
Low EMI Network LAN Clock
PIN DESCRIPTIONS
Name
XIN XOUT/50MHz_OE 50MHz/FS(0:2) 50MHz/SS0 FS3 25MHz/125MHz SDRAMx2 25MHz/100MHz VDD GND
Number
2 3 6,8,9,11 10 13,15 18,20 22 1,5,12, 16,17,23,24 4,7,14,19,21
Type
I B B I O O O P P
Description
25MHz fundamental crystal input (20pF C L parallel resonant). C L have been integrated into the chip. No external C L capacitor is required. Crystal connection pin. At power-up, this pin latches 50MHz_OE (output enable selector for all 50MHz outputs. Disabled when 50MHz_OE is logical zero. Has 120k Ω internal pull up resistor. Bi-directional pins. 50MHz outputs. These pins latch FS(0:2) and SS0 at power-up. 60k Ω internal pull up resistors on pins 6 and 8. Tri-level input pin. FS3 input put. 25MHz (reference) or 125MHz outputs. Can be disabled with FS3 = 1. SDRAM outputs with double drive strength determined by FS(0:1) value. 25MHz (reference) or 100MHz output. Can be disabled with FS2 = M. 3.3V power supply. Ground.
SPREAD SPECTRUM SELECTION TABLE
SS0
0 M 1
SST modulation
± 0.75% center OFF ± 0.5% center
FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies
The PLL650-02 provides selectable spread spectrum modulation and selectable output frequencies. Selection is made by connecting specific pins to a logical “zero” or “one”, or by leaving them not connected (tri-level inputs or internal pull-up) according to the frequency and spread spectrum selection tables shown on pages 1 and 2 respectively. In order to reduce pin usage, the PLL650-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 (Connect to GND), 1 (Connect to VDD), M (Do not connect). Thus, unlike the two-level selection pins, the tri-level input pins are in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to GND. Likewise, in order to connect to a logical “one” the pin must be connected to VDD. Pin 3 (XOUT/50MHz_OE) is a bi-directional pin used to disable the 50MHz output pins. Pin 6 (FS0) and pin 8 (FS1) are bidirectional pins used to select the SDRAM output frequency upon power-up. Pin 9 (FS2) and pin 11 (FS3) are tri-level bidirectional pins used to select the output frequency of pins 13, 15 and 22, as shown in the frequency table on page 1. After the input signals have been latched, pins 6, 8, 9, and 11 serve as 50 MHz frequency outputs.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 05/02/01 Page 2
PLL650-02
Connecting a bi-directional pin
Low EMI Network LAN Clock
A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unid.