PLL620-80

m Preliminary PLL620-80 o c Low Phase .Noise XO (for 27-65MHz Fund. Or 3 O.T. Crystals) U 4 t e FEATURES DIE CONFIGURATION e h S Fundamental or 3 overtone 27MHz to 65MHz Crystal. ta Outputa – 65MHz (no PLL). D range: 27MHz Complementary outputs: CMOS, PECL or LVDS. . w Selectable OE Logic (enable high or enable low). w Integrated variable capacitors. w Supports 3.3V-Power Supply. rd rd 65 mil (1550,1475) 25 24 22 21 19 18 17 26 16 27 15 28 14 Available in die form. Thickness 10 mil. DESCRIPTIONS PLL620-80 is an XO IC specifically designed to work with crystals between 27MHz and 65MHz. It accepts fundamental crystals, and also 3 rd overtone crystals (requires external resistor). It achieves very low current into the crystal resulting in better overall stability. It features a selectable OE logic, as well as selectable output buffers (CMOS, LVDS or PECL). BLOCK DIAGRAM XIN XOUT Oscillator Amplifier m o .c U 4 t e e h S a t a .D w w w 62 mil 13 12 11 30 31 9 1 2 3 4 5 6 8 Y (0,0) X SPECIFICATIONS Size Reverse side Value GND 80 micron x 80 micron Thickness OE Q Q OUTPUT SELECTION AND ENABLE Pad #18 0 0 1 1 Pad #25 OUTSEL0 0 1 0 1 PLL620-80 (default) State OE_SELECT (Pad #9) 0 1 (Default) Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1” No connection results to “default” setting through internal pull-up/-down. Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if O...