PLL620-20

m Preliminary PLL620-20 o c . Low Phase Noise XO (for HF Fund. and 3 O.T.) U t4 e FEATURES DIE CONFIGURATION e h S Fundamental Mode Crystal. 100MHz to 200MHz a Output range: 100 – 200MHz (no multiplication). at design High yield support up to 2pF string D at 200MHz. capacitance . w Available outputs: PECL, or LVDS. w Supports 3.3V-Power Supply. w Available in die form. rd 65 mil (1550,1475) 25 24 23 22 21 20 19 18 17 26 16 27 15 28 14 Thickness 10 mil. DESCRIPTIONS PLL620-20 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies. BLOCK DIAGRAM Vin X+ XOscillator Amplifier m o .c U 4 t e e h S a t a .D w w w 62 mil 13 29 12 11 30 10 9 31 1 2 3 4 5 6 7 8 Y (0,0) X DIE SPECIFICATIONS Name Size Reverse side Value 62 x 65 mil GND Pad dimensions Thickness 80 micron x 80 micron 10 mil OE Q OUTPUT SELECTION AND ENABLE Pad #9 OUTSEL 0 1 Selected Output Q LVDS PECL (default) PLL620-20 Pad #9 OUTSEL 0 1 Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OUTSEL (pad #9) is “1” Logical states defined by CMOS levels if OUTSEL is “0” Pad #30 OE_CTRL 0 1 0 1 ...