PLL650-10

FEATURES w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. Two outputs fixed at 125MHz.. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. w .D at h S a t e e 4U . m o c PRELIMINARY PLL650-10 Network LAN Clock for Gigabit Ethernet PIN CONFIGURATION XIN XOUT GND 125MHz 1 2 3 4 8 7 6 5 VDD GND VDD 125MHz P LL 650-10 DESCRIPTIONS The PLL 650-10 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25MHz crystal, and produces multiple output clocks for networking chips, and ASICs. BLOCK DIAGRAM XIN XO UT XTAL OS C w w w .D C ontrol Logic t a S a e h t e U 4 .c m o 125MHz 125MHz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 w w w .D a t a e h S 4 t e U . m o c Rev 12/10/02 Page 1 PRELIMINARY PLL650-10 Network LAN Clock for Gigabit Ethernet PIN DESCRIPTIONS Name XIN XOUT 125MHz VDD GND Number 1 2 4,5 6,8 3,7 Type I O O P P Description 25MHz fundamental crystal input (20pF C L parallel resonant). C L have been integrated into the chip. No external C L capacitor is required. Crystal connection pin. 125MHz outputs. 3.3V power supply Ground. 47745 Fremont Blvd., Fremont, California 94...