PLL650-09

FEATURES w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 4 outputs fixed at 50MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. w .D at h S a t e e 4U . m o c PLL650-09 Low Cost Network LAN Clock PIN CONFIGURATION XIN XOUT G ND VDD 50MHz G ND 50MHz 1 2 16 15 VDD VDD N/C G ND G ND GND VDD P LL 650-09 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTIONS The PLL 650-09 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips. 50MHz BLOCK DIAGRAM XIN XOUT XTAL OS C w w w .D t a S a e h t e 4 U 4 .c m o 50MHz 50MHz C ontrol Logic 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 w w w .D a t a e h S 4 t e U . m o c Rev 09/19/02 Page 1 PLL650-09 Low Cost Network LAN Clock PIN DESCRIPTIONS Name XIN XOUT 50MHz N/C VDD GND Number 1 2 5,7,8,9 14 4,10,15,16 3,6,11,12,13 Type I O O P P Description 25MHz fundamental crystal input (20pF C L parallel resonant). C L have been integrated into the chip. No external C L capacitor is required. Crystal output connection pin. 50MHz outputs. No connection. 3.3V power supply. Ground. 4774...