Document
m Preliminary PLL701-01/02/04/06 o c . Low EMI Spread Spectrum Multiplier Clock U 4 t e FEATURES PIN CONFIGURATION e h Clock Generator with selectable • Spread Spectrum S multiplier from ta 1x to 6x outputs. • Outputa frequency ranges: 10MHz to 180MHz. • Modulates external clocks including crystals, .D oscillators crystal and ceramic resonators. w • Selectable Center Spread Modulation. w • Selectable Modulation rate. w• TTL/CMOS compatible outputs.
XIN/FIN 1 2 3 4 8 7 6 5 VDD
PLL701-0X
XOUT/SD*^ SC0^
SC2^
FOUT GND
• • •
3.3V Operating Voltage. Low short term jitter. Available in 8-Pin 150mil SOIC.
DESCRIPTIONS
The PLL701-01/02/04/06 is a Spread Spectrum Clock Generator designed for the purpose of reducing EMI in high-speed digital systems. Any output frequency from 10 to 180MHz can be selected by programming 6 multiplier modes. The device is designed to operate over a very wide range of input frequencies and provides 1x to 6x modulated clock outputs.
OUTPUT CLOCK (FOUT) SELECTION
FOUT (-01)
X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1 X1
SD
1 1 0 1 0 1 0 1 0 1 0 1 0 1
SC2
0 0 0 0 0 0 0 1 1 1 1 1 1 1
SC1
0 0 0 1 1 1 1 0 0 0 0 1 1 1
m o .c U 4 t e e h S a t a .D w w w
XIN/FIN = 10 ~ 30 MHz
Note:
SC1^
^: Internal pull-up resistor (120k Ω for SD, 30 k Ω for SC0-SC2). *: The value of SD is latched upon powerup. The internal pull-up resistor results in a default high value when no pull-down resistor is connected to this pin (recommended external pull-down resistor of 27 k Ω ).
SC0
0 1 1 0 0 1 1 0 0 1 1 0 0 1
FOUT (-02)
X2 X2 X2 X2 X2 X2 X2 X2 X2 X2 X2 X2 X2 X2
FOUT (-04)
X4 X4 X4 X4 X4 X4 X4 X4 X4 X4 X4 X4 X4 X4
FOUT (-06)
X6 X6 X6 X6 X6 X6 X6 X6 X6 X6 X6 X6 X6 X6
SST Modulation Freq.
Magnitude
0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 3.50% OFF
Type
Notes: C: Center Spread. A: Asymmetric Spread. D: Down Spread.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
m o .c Fin / 512 U 4 t e e h S a at .D w w w
Rev 09/11/02 Page 1
C C D C A C A C A C A C A
± 0.25% ± 0.5% -1.0% ± 0.75% +0.25% ~ -1.25% ± 1.0% +0.5% ~ -1.5% ± 1.25% +0.75% ~ -1.75% ± 1.5% +1.0% ~ -2.0% ± 1.75% +1.25% ~ -2.25%
Preliminary
PLL701-01/02/04/06
Low EMI Spread Spectrum Multiplier Clock
BLOCK DIAGRAM
XIN XOUT
VDD XTAL OSC PLL SST FOUT
SC(0:2)
Control Logic
PIN DESCRIPTIONS
Name
XIN/FIN XOUT/SD SC0 SC1 SC2 VDD FOUT GND
Number
1 2 3 4 7 8 6 5
Type
I B I I I P O P
Description
Crystal input to be connected to fundamental parallel mode crystal.(C L =18pF) or clock input. At power-up, this pin is an input pin to select modulation rate. After input sampling, this pin is crystal output. Has internal pull up resistor. Digital control input to select output frequency. Has internal pull-up. Digital control input to select output frequency. Has internal pull-up. Digital control input to select output frequency. Has internal pull-up. 3.3V Power Supply. Modulated Clock Frequency Output. The frequency before modulation is synthesized by mul.