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ICS9112-18

Part Number	ICS9112-18
Manufacturer	Integrated Circuit Systems
Description	Zero Delay / Low Skew Buffer
Published	Feb 10, 2006
Detailed Description	Description w w The ICS9112-18 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buf...
Datasheet	ICS9112-18 PDF File

Overview

Description w w The ICS9112-18 is a low jitter, low skew, high performance Phase Lock Loop (PLL) based zero delay buffer for high speed applications.
Based on ICS’ proprietary low jitter PLL techniques, the device provides eight low skew outputs at speeds up to 160 MHz at 3.
3V.
The ICS9112-18 includes a bank of four outputs running at 1/2X.
In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of all eight outputs.
Compared to competitive CMOS devices, the ICS9112-18 has the lowest jitter.
a D .
w ta Sh ee U 4 t .
c om ICS9112-18 ZERO DELAY, LOW SKEW BUFFER Features • • • • • • • Packaged in 16 pin SOIC Zero input-output delay Four 1X outputs p...

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