MT46V128M8

m 1Gb: x4, x8, x16 DDR SDRAM o Features c . U 4 t Double Data Rate (DDR) SDRAM e e– 64 Meg x 4 x 4 banks MT46V256M4 h S – 32 Meg x 8 x 4 banks MT46V128M8 a MT46V64M16 at – 16 Meg x 16 x 4 banks .D w w Features Options Marking w For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/datasheets VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V VDD = VDDQ = +2.6V ±0.1V (DDR400) Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte) Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data (x16 has two –one per byte) Programmable burst lengths: 2, 4, or 8 Auto Refresh and Self Refresh Modes Longer lead TSOP for improved reliability (OCPL) 2.5V I/O (SSTL_2 compatible) Concurrent auto precharge option is supported tRAS lockout supported (tRAP = tRCD) Table 1: Addressing Configuration Configuration Refresh Count Row Addressing Bank Addressing Column Addressing m o .c U 4 t e e h S a t a .D w w w Configuration 256 Meg x 4 (64 Meg x 4 x 4 banks) 128 Meg x 8 (32 Meg x 8 x 4 banks) 64 Meg x 16 (16 Meg x 16 x 4 banks)1 Plastic Package – OCPL 66-p...