ST10R167

ST10R167 16-BIT ROMLESS MCU s HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE – 80ns INSTRUCTION CYCLE TIME @ 25MHz CLK – 400ns 16 X 16-BIT MULTIPLICATION – 800ns 32 / 16-BIT DIVISION – ENHANCE D BOOLEAN BIT MANIPULATION FACILITIES – ADDITIONAL INSTRUCTIONS TO SUPPOR T HLL AND OPERATING SYSTEMS – SINGLE-CYCL E CONT EXT SWITCHING SUPPORT MEMORY ORGANIZATION – UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN) – 2K BYTE ON-CHIP INTERNAL RAM (IRAM) – 2K BYTE ON-CHIP EXTENSION RAM (XRAM) FAST AND FLEXIBLE BUS – PROGRAMMABLE EXTERNAL BUS CHARA CTERISTICS FOR DIFFERENT ADDRESS RANGES – 8-BIT OR 16-BIT EXTERNAL DATA BUS – MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRE SS/DATA BUSES – FIVE PROGRAMMABLE CHIP-SELECT SIGNALS – HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT INTERRUPT – 8-CHANNEL PERIPHERAL EVENT CONTROLLER FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA TRANSFER – 16-PRIORITY-LEVEL INTERRUPT SYSTE M WITH 56 SOURCES, SAMPLE-RATE DOWN TO 40ns TIMERS – TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS – TWO 16-CHANNEL CAPTURE/COMPARE UNITS A/D CONVERTER – 16-CHANN EL 10-BIT – 7.76µs CONVERSION TIME FAIL-SAFE PROTECTION – PROGRAMMABLE WATCHDOG TIMER – OSCILLATOR WATCHDOG ON-CHIP CAN 2.0B INTERFACE ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION – ON-CHIP PLL – DIRECT OR PRESCALE D CLOCK INPUT s PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack) s s s s s s s s UP TO 111 GENERAL PURPOSE I/O LINES – INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIA L ...