M32L1632512A

m o .c U SGRAM 4 t e e h S a FEATURES at 3.3V power supply y JEDEC standard y LVTTL .D compatible with multiplexed address w bank / Pulse RAS y Dual yw MRS cycle with address key programs w - CAS Latency ( 2, 3 ) y y y y y y - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM 0-3 for byte masking Auto & self refresh 32ms refresh period (2K cycle) 100 pin QFP ESMT M32L1632512A 256K x 32 Bit x 2 Banks Synchronous Graphic RAM GENERAL DESCRIPTION The M32L1632512A is 16, 777, 216 bits synchronous high data rate Dynamic RAM organized as 2 x 262, 144 words by 32 bits, fabricated with ESMT’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies , programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphic systems. Graphic Features y SMRS cycle - Load mask register - Load color register y Write Per Bit y Block Write (8 Columns) m o .c U 4 t e e h S a t a .D w w w ORDERING INFORMATION Part NO. Cycle time 5ns M32L1632512A-5Q 200MHz M32L1632512A-5SQ M32L1632512A-6Q 5ns 200MHz 6ns 166MHz M32L1632512A-6SQ M32L1632512A-7Q 6ns 166...