MT4LC16M4A7

16 MEG x 4 FPM DRAM DRAM FEATURES Single +3.3V ±0.3V power supply Industry-standard x4 pinout, timing, functions, and packages 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8) High-performance CMOS silicon-gate process All inputs, outputs and clocks are LVTTL-compatible FAST-PAGE-MODE (FPM) access 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms Optional self refresh (S) for low-power data retention MT4LC16M4A7, MT4LC16M4T8 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ3 DQ2 NC NC NC CAS# OE# A12/NC** A11 A10 A9 A8 A7 A6 VSS OPTIONS Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) Timing 50ns access 60ns access Refresh Rates Standard Refresh Self Refresh (128ms period) MARKING T8 A7 DJ TG -5 -6 None S* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC VSS DQ0 DQ3 DQ1 DQ2 NC NC NC NC NC NC NC WE# CAS# RAS# OE# A0 A12/NC** A1 A11 A2 A10 A3 A9 A4 A5 A8 VCC A7 A6 VSS **A12 on A7 version and NC on T8 version 16 MEG x 4 FPM DRAM PART NUMBERS PART NUMBER MT4LC16M4A7DJ-x MT4LC16M4A7DJ-x S MT4LC16M4A7TG-x MT4LC16M4A7TG-x S MT4LC16M4T8DJ-x MT4LC16M4T8DJ-x S M...