Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
High–Performance Silicon–Gate...
Description
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 72 FETs or 18 Equivalent Gates
MC54/74HC132A
J SUFFIX CERAMIC PACKAGE CASE 632–08
1
14
14 1
N SUFFIX PLASTIC PACKAGE CASE 646–06
14 1
D SUFFIX SOIC PACKAGE CASE 751A–03
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD Ceramic Plastic SOIC
LOGIC DIAGRAM
A1 1 3 B1 A2 2 4 6 B2 A3 5 Y = AB 9 8 B3 10 Y3 Y2
PIN ASSIGNMENT
Y1 A1 B1 Y1 A2 B2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3
FUNCTION TABLE
Inputs Output B L H L H Y H H H L A 11 L L H H
A4 12 Y4
B4
13 PIN 14 = VCC PIN 7 = GND
10/95
© Motorola, Inc. 1995
1
REV 6
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