Hex D Flip-Flop witth Common Clock and Reset
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Flip-Flop with Common Clock and Reset
High–Performance Silicon–Gate CMOS
T...
Description
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Flip-Flop with Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC54/74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active–low. Output Drive Capability: 10 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 µA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 162 FETs or 40.5 Equivalent Gates LOGIC DIAGRAM
D0 3 D1 4 DATA INPUTS D2 6 D3 11 D4 13 14 D5 2 Q0 5 Q1 7 Q2 10 Q3 12 Q4 15 Q5
MC54/74HC174A
J SUFFIX CERAMIC PACKAGE CASE 620–10
1
16
16 1
N SUFFIX PLASTIC PACKAGE CASE 648–08
16 1
D SUFFIX SOIC PACKAGE CASE 751B–05
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD Ceramic Plastic SOIC
NONINVERTING OUTPUTS
PIN ASSIGNMENT
RESET Q0 D0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q5 D5 D4 Q4 D3 Q3 CLOCK
CLOCK 9
D1 Q1
RESET 1
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ
PIN 16 = VCC PIN 8 = GND Design Criteria Value 40.5 1.5 5.0 Un...
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