Part Number |
MPC2106C |
Manufacturers |
Motorola |
Logo |
|
Description |
(MPC2105C / MPC2106C) 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
Datasheet |
MPC2106C Datasheet (PDF) |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms
The MPC2105C and the MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format. The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the .