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ICS2008B Dataheets PDF



Part Number ICS2008B
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description SMPTE Time Code Receiver/Generator
Datasheet ICS2008B DatasheetICS2008B Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS2008B SMPTE Time Code Receiver/Generator General Description The ICS2008B, SMPTE Time Code Receiver / Generator chip, is a VLSI device designed in a low power CMOS process. This device provides the timing coordination for Multimedia sight and sound events. Although it is aimed at a PC Multimedia environment, the ICS2008B is easily integrated into products requiring SMPTE time code generation and/or reception in LTC (Longitudinal Time Code) and/or VITC (Verti.

  ICS2008B   ICS2008B


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Integrated Circuit Systems, Inc. ICS2008B SMPTE Time Code Receiver/Generator General Description The ICS2008B, SMPTE Time Code Receiver / Generator chip, is a VLSI device designed in a low power CMOS process. This device provides the timing coordination for Multimedia sight and sound events. Although it is aimed at a PC Multimedia environment, the ICS2008B is easily integrated into products requiring SMPTE time code generation and/or reception in LTC (Longitudinal Time Code) and/or VITC (Vertical Interval Time Code) formats and MTC (MIDI Time Code) translation. Taking its input from composite video, S-Video, or an audio track, the ICS2008B can read SMPTE time code in VITC and LTC formats. Time code output formats are LTC and VITC. All are available simultaneously. A UART is provided for the user to support MTC or tape transport control. The processor interface is compatible with the IBM PC and ISA bus compatible computers and is easily interfaced to other processors and micro-controllers. The ICS2008B is an improved version of the ICS2008, with additional features and capabilities. ICS2008 ICS2008B 2008 2008B • Features • • • • • Meets SMPTE VITC Specifications Meets SMPTE and EBU LTC Specifications Time Code Burn-in Window – Programmable position, size and character attributes LTC edge rate control – Conforms to EBU Tr and Tf Specifications Internal and external sync sources – Genlock to video or house sync inputs – Improved video timing lock during VCR pause and shuttle modes – Internally generated timing from oscillator input – External click input – Internal Timer Allows 1/4 Frame MIDI Time Code Messages LTC and VITC Generators – Real Time SMPTE Rates: 30Hz, 29.97Hz, 25Hz, 24Hz – Time Code Modes Drop Frame and Color Frame – VITC can be inserted on two lines from 10-40 (SMPTE specifies lines 10-20) – Jam Sync, freewheeling, error bypass/correction, and plus-one-frame capability LTC Receiver – Synchronize bit rates from 1/30th nominal to 80X nominal playback speed. VITC Receiver – Reads code from any or all selected scan lines. – VITC search mode, will search through VBI lines until VITC is found. New UART frequency of 38.4 K for tape transport control Block Diagram • • • ICS2008B Rev D 4/05/05 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS2008B Package Pinouts LTCIN+ LTCINCLICK FRAME RESET INTR D7 6 5 4 3 2 LTCOUT LFC XTAL2 XTAL1 AVDD AVSS COUT YOUT C2 Y2 C1 7 8 9 10 11 12 13 14 15 16 17 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D2 D1 D0 IOW* VDD VSS IOR* UARTCS* SMPTECS* A1 A0 18 19 20 21 22 23 24 25 26 27 28 Y1 STHRESH CTHRESH DTHRESH RXD CTS* TXD D6 D5 D4 D3 D2 D1 D0 IOW* VDD VSS IOR* UARTCS* SMPTECS* A1 A0 RTS* LRCLK VITCGATE VITCOUT 2 LTCOUT LFC XTAL2 XTAL1 AVDD AVSS COUT YOUT C2 Y2 C1 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 31 3 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 Y1 STHRESH CTHRESH DTHRESH RXD CTS* TXD ICS2008B Rev D 4/05/05 LTCIN+ LTCINCLICK FRAME RESET INTR D7 RTS* LRCLK VITCGATE VITCOUT D6 D5 D4 D3 ICS2008B Pin Descriptions PIN NUMBER TQFP PLCC 12, 10 11, 9 15 13 14 8 7 41 42 44 43 1 20 22 21 18 16 17 19 4 3 2 24, 23 27 30 25 26 40 38–31 39 5 6 29 28 18, 16 17, 15 PIN NAME Y1, Y2 C1, C2 TYPE AI AI AI AI AI AO AO AI AI AI AI AO O O O O I I O I O AI I I I I I I I/O O P P P P DESC RIPTI ON Video inputs from camera or other source. NOTE: This is also the Y (Luma) input for S-VHS and HI-8 systems. C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this pin should be tied to its respective Y input. Data Threshold bypass input. SYNC Threshold bypass input. Clamp Threshold bypass input. Video output. This is also the Y (Luma) output in S-Video mode. C (Chroma) output for S-VHS and HI-8 systems. Color Frame A/B input. This input is self biased (See Applications). LTC SYNC input. This input is self biased (See Applications). SMPTE LTC input+. This input is self biased (See Applications). SMPTE LTC input–. This input is self biased (See Applications). SMPTE LTC output SMPTE LTC receive clock output. SMPTE VITC output to video mixer circuit. VITC gate indicates VITC code is being output for video overlay. UART Transmit data UART Receive data Clear to Send Ready to Send 14.318 MHz crystal input. 14.318 MHz crystal oscillator output. Tie to +5 VDC Address bus Read Enable (active low) Write Enable (active low) SMPTE port chip select (active low) UART chip select (active low) Master reset (active high) Bi-directional data bus Interrupt Request (active high) Analog VDD Analog Ground Digital VDD Digital 21 DTHRESH 19 STHRESH 20 CTHRESH 14 Y OUT 13 C OUT 3 FRAME 4 CLICK 6 LTCIN+ 5 LTCIN– 7 LTCOUT 26 LRCLK 28 VITCOUT 27 VITCGATE 24 TxD 22 RxD 23 CTS* 25 RTS* 10 XTAL1 9 XTAL2 8 LFC 30, 29 A1-A0 33 IOR* 36.


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