NB6L11

NB6L11 2.5V/3.3V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the device is optimized for the systems that require LOW skew, LOW jitter and LOW power consumption. Differential input can be configured to accept single−ended signal by applying an external reference voltage to unused complimentary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML, or LVDS. The outputs are 800 mV ECL signals. Maximum Input Clock Frequency w 6 GHz Typical Maximum Input Data Rate w 6 Gb/s Typical Low 14 mA Typical Power Supply Current 150 ps Typical Propagation Delay 5 ps Typical Within Device Skew 75 ps Typical Rise/Fall Times PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V Open Input Default State http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO−8 D SUFFIX CASE 751 6L11 ALYW 1 8 8 1 TSSOP−8 DT SUFFIX CASE 948R A L Y W = Assembly Location = Wafer Lot = Year = Work Week 6L11 ALYW 1 Q Outputs Will Default LOW with Inputs Open or at VEE LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input Compatible *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device NB6L11D NB6L11DR2 NB6L11DT** NB6L11DTR2** Package SO−8 S...