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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
Product Preview LCD Segment / Common Driver with Controller
CMOS
SSD1812 is a single-chip CMOS LCD driver with controller for liquid crystal dotmatrix graphic display system. It consists of 187 high voltage driving output pins for driving 132 Segments, 54 Commons and 1 Icon Driving-Common.
SSD1812
TAB
SSD1812 displays data directly from its internal 132 X 65 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through a software selectable 6800-/8080-series compatible Parallel Interface or Serial Peripheral Interface. SSD1812 embeds a DC-DC Converter, an On-Chip Bias Divider and an On-Chip Oscillator which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1812 is suitable for any portable battery-driven applications requiring a long operation period and a compact size.
Gold Bump Die
ORDERING INFORMATION SSD1812Z SSD1812TR Gold Bump Die TAB
• • • • • • • • • • • • • • • • • • •
Single Supply Operation, 1.8 V - 3.5V Minimum -12.0V LCD Driving Output Voltage Low Current Sleep Mode On-Chip Voltage Generator / External Power Supply 2X / 3X / 4X On-Chip DC-DC Converter On-Chip Oscillator Programmable Multiplex ratio [1Mux - 55Mux] On-Chip Smart Bias Divider Programmable 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9 bias ratio 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface and Serial Peripheral Interface On-Chip 132 x 65 Graphic Display Data RAM Re-mapping of Row and Column Drivers Vertical Scrolling Display Offset Control RAM Page Blinking 64 Level Internal Contrast Control External Contrast Control Selectable LCD Driving Voltage Temperature Coefficients (8 settings) Available in Gold Bump Die and Standard TAB (Tape Automated Bonding) Package
This document contains information on a new product under development. Solomon reserves the right to change or discontinue this product without notice.
Copyright © 1999 Solomon Technolgoy Corp.
REV 1.2 12/99
Block Diagram
ICONS
ROW0 to ROW63
SEG0~SEG131
HV Buffer Cell Level Shifter
Level Selector
VL6 VL2 VDD Display Timing Generator VF LCD Driving Voltage Generator 2X / 3X / 4X DC/DC Converter, Voltage Regulator, Smart Bias Divider, Contrast Control, Temperature Compensation VEE C1P C2P C1N C2N C3N IRS HPM VFS VSS1
187 Bit Latch MSTAT M
DOF M/S
CL CLS
Oscillator
GDDRAM 132 X 65 Bits
Command Decoder
VSS VDD Command Interface Parallel / Serial Interface
RES P/S CS1 CS2 D/C
R/W C68/80 M/S E (RD) (WR)
D7 D6 D5 D4 D3 D2 D1 D 0 (SDA) (SCK)
SSD1812 2
REV 1.2 12/99
SOLOMON
178 177 176 175
Dummy /CS1 /RES D/C R/W(/WR) D0 (SDA) D1 (SCK) D2 D3 D4 D5 D6 D7 VDD VSS VEE C3N C1P C1N C2N C2P VL2 VL3 VL4 VL5 VL6 VF P/S Dummy
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
:: :: ::
Dummy Dummy Dummy ICONS ROW58 ROW57 R0W56
153 152 151 150 149 148
ROW34 ROW33 ROW32 SEG95 SEG94 SEG93
:: :: ::
57 56 55 54 53 52
SEG2 SEG1 SEG0 ROW0 ROW1 ROW2
:: :: ::
30 29 28
ROW24 ROW25 ROW26 Dummy Dummy Dummy
SSD1812T Pin Assignment (Copper View)
SOLOMON
REV 1.2 12/99
SSD1812 3
ICONS ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20
137 Center: 3816.05, 305.2 Size: 100.1u x 100.1u
115 Center: 3819.2, -419.2 Size: 99.75u x 99.75u
: :
SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131
: :
268
1
ROW20 ROW21 : : ROW30 ROW31 VDD IRS VSS /HPM VDD P/S C68/80 VSS CLS M/S VDD NC NC VDD VDD VF VF VL6 VL6 VL6 VL5 VL5 VL4 VL4 VL4 VL3 VL3 VL3 VL2 VL2 VDD VDD VFS VFS VSS VSS C2P C2P C2P C2N C2N C2N C2N C1N C1N C1N C1P C1P C1P C3N C3N C3N C3N VEE VEE VEE VEE VSS1 VSS1 VSS1 VSS1 VSS VSS VSS VDD VDD VDD VDD D7 (SDA) D6 (SCK) D5 D4 D3 D2 D1 D0 VDD E(/RD) R/W(/WR) VSS D/C /RES VDD CS2 /CS1 VSS /DOF CL M MSTAT NC ICONS ROW63 ROW62 ROW61 : : ROW54 ROW53
Center: 3701.075, -304.5 Radius: 50.925u
Gold Bump Alignment Mark This alignment mark contains gold nump for IC bumping process alignment and IC identifications. No conductive tracks should be laid underneath this mark to avoid short circuit.
Note: Coordinates and Size of all alignment marks are in unit um and w.r.t. center of the chip.
Y
Center: -3380.625, 205.625 Size: 99.75u x 99.75u
(0,0)
Center: 389.725, -201.6 Radius: 27.125u
x
PIN #1 Die Size: 10.977mm X 1.912mm Die Thickness: 533 +/-25um Bump Pitch: 76.2 um [Min] Bump Height: Nominal 18um
SSD1812Z Die Pin Assignment SOLOMON
SSD1812 4
REV 1.2 12/99
ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52
Table 1. ROW pins assignment for COM signals in Programmable Multiplex Ratio [On power-on-reset, SSD1812 is set to 54 Multiplex]
Die.