DatasheetsPDF.com

ICS302 Dataheets PDF



Part Number ICS302
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description (ICS300 - ICS302) QTClock Quick Turn Clock Synthesizer
Datasheet ICS302 DatasheetICS302 Datasheet (PDF)

ICS300/ICS301/ICS302 QTClock™ Quick Turn Clock Synthesizer Description The ICS300 and ICS301 QTClocks™ generate a high quality, high frequency clock output and a reference from a low frequency crystal or clock input. They are designed to replace crystals and crystal oscillators in most electronic systems. The ICS302 can accept a higher frequency clock input to generate up to 200 MHz. The devices contain a One Time Programmable (OTP) ROM which is factory programmed with the PLL divider values to .

  ICS302   ICS302


Document
ICS300/ICS301/ICS302 QTClock™ Quick Turn Clock Synthesizer Description The ICS300 and ICS301 QTClocks™ generate a high quality, high frequency clock output and a reference from a low frequency crystal or clock input. They are designed to replace crystals and crystal oscillators in most electronic systems. The ICS302 can accept a higher frequency clock input to generate up to 200 MHz. The devices contain a One Time Programmable (OTP) ROM which is factory programmed with the PLL divider values to output a broad range of frequencies, from 6 to 200 MHz, allowing customer requests for different frequencies to be shipped in 1-3 days. Using Phase-Locked-Loop (PLL) techniques, the devices run from a standard fundamental mode, inexpensive crystal, or clock. They are smaller and less expensive than one oscillator. Features • Packaged as 8 pin SOIC • Quick turn frequency programming allows samples in one to three days • Replaces nearly any crystal or oscillator • ICS300 produces up to 100 MHz at 3.3V, ICS301 produces up to 200 MHz at 3.3V ICS302 accepts up to 125 MHz clock input • Easy to cascade with ICS5xx series • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 2 - 125 MHz • Low jitter - 50 ps one sigma • Compatible with all popular CPUs • Duty cycle of 45/55 • Operating voltages of 3.0 to 5.5V • Full CMOS level outputs with 25mA drive capability at TTL levels • Tri-state output + PLL power down pin • Advanced, low power CMOS process Block Diagram VDD GND Crystal or clock input OTP ROM with PLL Divider Values X1/ICLK PLL Clock Synthesis and Control Circuitry Output Buffer CLK Crystal Oscillator X2 Divide Logic and Output Buffer REF PDTS (both outputs and PLL) MDS 300QT E 1 Revision 111000 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com ICS300/ICS301/ICS302 QTClock™ Quick Turn Clock Synthesizer Pin Assignments X1/ICLK VDD GND REF GND VDD GND REF 8 1 ICS300 7 2 3 ICS301 6 4 5 8 1 2 ICS302 7 3 6 4 5 X2 PDTS DC CLK ICLK PDTS DC CLK REF Clock Options REF Reference Reference/2 CLK/2 Off Comments Buffered oscillator output Oscillator frequency divided by two CLK frequency divided by two Output stopped low. Lowest jitter Pin Descriptions Number Number Name Type Description 300/1 302 1 8 X1/ICLK I Crystal connection or clock input. Clock only on ICS302. 2 2 VDD P Connect to +3.3V or +5V. 3 1, 3 GND P Connect to ground. 4 4 REF O Buffered crystal oscillator output clock, or variation per REF clock options table above. 5 5 CLK O Clock output. Fixed frequency between 6 and 200 MHz programmed at factory. 6 6 DC Don't Connect anything to this pin. 7 7 PDTS I Powers down PLL, and puts both outputs into high impedance state, when low. 8 X2 O Crystal connection. Leave unconnected for clock input. Key: I = Input, O = output, P = power supply connection Device Configuration The specification is complete when the ICS300/301/302 QTClock Order Form accompanies this data sheet. The order form lists the input, REF, and CLK actual frequencies, as well as any other available options. This unique configuration is given a two character alphanumeric programming code, which must be specified when referring to samples. External Components / Crystal Selection The ICS300/301/302 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected close to the ICS300/301/302 to minimize lead inductance. No external power supply filtering is required for this device. A 33Ω terminating resistor can be used next to the CLK and REF pins. The total on-chip capacitance is approximately 16 pF, so a parallel resonant, fundamental mode crystal should be used. For crystals with a specified load capacitance greater than 16 pF, crystal capacitors can be connected from each of the pins X1 and X2 to Ground. The value (in pF) of these crystal caps should be = (CL -16)*2, where CL is the crystal load capacitance in pF. These external capacitors are only required for applications where the exact frequency is critical. For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either). MDS 300QT E 2 Revision 111000 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com ICS300/ICS301/ICS302 QTClock™ Quick Turn Clock Synthesizer Electrical Specifications Parameter Conditions Minimum Typical ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted) Operating Voltage, VDD 3 Input High Voltage, VIH, ICLK only ICLK (Pin 1) (VDD/2)+1 VDD/2 Input Low Voltage, VIL, ICLK only ICLK (Pin 1) VDD/2 Input High Voltage, VIH PDTS 2 Input Low Voltage, VIL PDTS Output High Voltage, VOH IOH=-4mA VDD-0.4 Output High Voltage.


ICS301 ICS302 ICS332


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)