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ICS9250-30 Dataheets PDF



Part Number ICS9250-30
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Frequency Generator & Integrated Buffers
Datasheet ICS9250-30 DatasheetICS9250-30 Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS9250-30 Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 810/810E and Solano type chipset Output Features: • 2 - CPUs @ 2.5V, up to 200MHz. • 13 - SDRAM @ 3.3V, up to 200MHz. • 3 - 3V66 @ 3.3V, 2x PCI MHz. • 8 - PCI @3.3V. • 1 - 48MHz, @3.3V fixed. • 1 - 24/48MHz @ 3.3V • 1 - REF @3.3V, 14.318MHz. Features: • Support PC133 SDRAM. • Up to 200MHz frequency support • Support power management th.

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Integrated Circuit Systems, Inc. ICS9250-30 Preliminary Product Preview Frequency Generator & Integrated Buffers for Celeron & PII/III™ Recommended Application: 810/810E and Solano type chipset Output Features: • 2 - CPUs @ 2.5V, up to 200MHz. • 13 - SDRAM @ 3.3V, up to 200MHz. • 3 - 3V66 @ 3.3V, 2x PCI MHz. • 8 - PCI @3.3V. • 1 - 48MHz, @3.3V fixed. • 1 - 24/48MHz @ 3.3V • 1 - REF @3.3V, 14.318MHz. Features: • Support PC133 SDRAM. • Up to 200MHz frequency support • Support power management through PD#. • Spread spectrum for EMI control (± 0.25% Center Spread or 0 to -0.5% down spread) • Uses external 14.318MHz crystal • FS pins for frequency select Key Specifications: • CPU Output Jitter: <250ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps • For group skew timing, please refer to the Group Timing Relationship Table. Pin Configuration VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1 *FS1/PCICLK1 1 *SEL24_48#/PCICLK2 GNDPCI PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GNDSDR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FS4* VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GNDLCPU GNDSDR SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 1 24_48MHz/FS2 * 1 48MHz/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 GNDSDR 1 56-Pin 300 mil SSOP 1. These pins will have 1.5 to 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs. Block Diagram PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum Functionality 48MHz 24_48MHz REF0 CPU DIVDER 2 CPUCLK [1:0] SDRAM DIVDER 12 SDRAM [11:0] SDRAM_F FS[4:0] PD# SEL24_48# SDATA SCLK Control Logic Config. Reg. IOAPIC DIVDER IOAPIC PCI DIVDER 8 PCICLK [7:0] FS4 FS3 FS2 FS1 FS0 CPU SDRAM 0 0 0 0 0 66.67 100.00 0 0 0 1 1 68.33 102.50 0 0 1 1 0 80.00 120.00 0 0 1 1 1 83.00 124.50 0 1 0 0 0 100.00 100.00 0 1 0 1 1 103.00 103.00 0 1 1 1 0 115.00 115.00 0 1 1 1 1 200.00 200.00 1 0 0 0 0 133.33 133.33 1 0 0 0 1 166.67 166.67 1 0 0 1 1 137.00 137.00 1 0 1 1 1 160.00 160.00 1 1 0 0 0 133.33 100.00 1 1 0 0 1 166.67 125.00 1 1 0 1 1 137.00 102.75 1 1 1 1 1 160.00 120.00 ICS9250-30 3V66 66.67 68.33 80.00 83.00 66.67 68.67 76.67 66.67 66.67 83.34 68.50 80.00 66.67 83.34 68.50 80.00 PCI 33.33 34.17 40.00 41.50 33.33 34.33 38.33 33.33 33.33 41.67 34.25 40.00 33.33 41.67 34.25 40.00 3V66 DIVDER 3 3V66 [2:0] For other hardware/I2C selectable frequencies please refer to Byte 0 frequency select register. 9250-30 Rev A 10/03/00 Third party brands and names are the property of their respective owners. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9250-30 Preliminary Product Preview General Description The ICS9250-30 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-30 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. Pin Configuration PIN P I N NA M E NUMBER 1, 9, 10, 18, 25, VDD 32, 33, 37, 45 2 3 4, 5, 14, 21, 28, 29, 36, 41, 49 8, 7, 6 11 12 20, 19, 17, 16, 15 13 SEL24_48# 22 23 24 34 PD# SCLK SDATA 48MHz FS3 FS2 24_48MHz SDRAM_F SDRAM [11:0] GNDL CPUCLK [1:0] VDDL IOAPIC FS4 REF0 IN IN IN IN OUT IN IN OUT OUT OUT PWR OUT PWR OUT IN OUT X1 X2 GND 3V66 [2:0] PCICLK0 FS0 PCICLK1 FS1 PCICLK [7:3] PCICLK2 TYPE PWR IN OUT PWR OUT OUT IN IN IN OUT OUT 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V PCI clock outputs Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs. Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs. 3.3V PCI clock output. Input logic select. When logic "0" is selected pin 35 = 48MHz When logic "1" is selected pin 35 = 24MHz. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input. Data input for I2C serial input. 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B . Logic inp.


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