A42MX24

v5.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 202 User-Programmable I/O Pins 5.6 ns Clock-to-Out 250 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode Commercial, Military Temperature and MIL-STD-883 Ceramic Packages QML Certification Ceramic Devices Available to DSCC SMD E ase of Int egr at io n Mixed Voltage Operation (5.0V or 3.3V I/O) Synthesis-Friendly Architecture to Support ASIC Design Methodologies Up to 100% Resource Utilization and 100% Pin Fixing Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Low Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing 5.0V and 3.3V Programmable PCI-Compliant I/O High P er f or m ance HiR el Feat ur es Commercial, Industrial, and Military Temperature Plastic Packages Pr od uc t P r o f i l e Capacity System Gates SRAM Bits Logic Modules 3,000 N/A — 295 — 9.5 ns N/A — 147 1 57 No No 6,000 N/A — 547 — 9.5 ns N/A — 273 1 69 No No 44, 68, 84 100 80 — — — 14,000 N/A 348 336 N/A 5.6 ns N/A 348 516 2 104 No No 84 100, 160 100 176 — — 24,000 N/A 624 608 N/A 6.1 ns N/A 624 928 2 140 No No 84 100, 160, 208 100 176 — — 36,000 N/A 954 912 24 6.1 ns N/A 954 1,410 2 176 Yes Yes 84 160, 208 — 176 — — 54,000 2,560 1,230 1...