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MAS3587F Dataheets PDF



Part Number MAS3587F
Manufacturers Micronas
Logo Micronas
Description MPEG Layer 3 Audio Encoder/Decoder
Datasheet MAS3587F DatasheetMAS3587F Datasheet (PDF)

ADVANCE INFORMATION MICRONAS MAS 3587F MPEG Layer 3 Audio Encoder/Decoder Edition March 2, 2001 6251-542-1AI MICRONAS MAS 3587F Contents Page 5 5 6 7 7 7 7 7 8 8 9 9 9 9 9 9 9 10 10 10 10 11 11 11 11 11 13 13 14 14 14 14 14 14 14 15 15 15 15 16 16 16 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.7. 2.7.1. 2.7.1.1. 2.7.2. 2.7.2.1. 2.7.2.2. 2.7.3. 2.7.4. 2.8. 2.8.1. 2.8.2. 2.9. 2.9.1. 2.9.2. 2.9.3. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.11.5. 2.11.6. 2.12. 2.13..

  MAS3587F   MAS3587F



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ADVANCE INFORMATION MICRONAS MAS 3587F MPEG Layer 3 Audio Encoder/Decoder Edition March 2, 2001 6251-542-1AI MICRONAS MAS 3587F Contents Page 5 5 6 7 7 7 7 7 8 8 9 9 9 9 9 9 9 10 10 10 10 11 11 11 11 11 13 13 14 14 14 14 14 14 14 15 15 15 15 16 16 16 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.7. 2.7.1. 2.7.1.1. 2.7.2. 2.7.2.1. 2.7.2.2. 2.7.3. 2.7.4. 2.8. 2.8.1. 2.8.2. 2.9. 2.9.1. 2.9.2. 2.9.3. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.11.5. 2.11.6. 2.12. 2.13. 2.13.1. 2.13.2. 2.13.3. 2.13.4. 2.13.5. Title Introduction Features Application Overview ADVANCE INFORMATION Functional Description of the MAS 3587F Overview Architecture of the MAS 3587F DSP Core RAM and Registers Firmware and Software Internal Program ROM and Firmware, MPEG-Encoding/Decoding Program Download Feature Audio Codec A/D Converter and Microphone Amplifier Baseband Processing Bass, Treble, and Loudness Micronas Dynamic Bass (MDB) Automatic Volume Control (AVC) Balance and Volume D/A Converters Output Amplifiers Clock Management DSP Clock Clock Output at CLKO Power Supply Concept Power Supply Regions DC/DC Converters Power Supply Configurations Battery Voltage Supervision Interfaces I2C Control Interface S/PDIF Input Interface S/PDIF Output Multiline Serial Audio Input (SDI, SDIB) Multiline Serial Output (SDO) Parallel Input/Output Interface (PIO) MPEG Synchronization Output Default Operation Stand-by Functions Power-Up of the DC/DC Converters and Reset Control of the Signal Processing Start-up of the Audio Codec Power-Down 2 Micronas ADVANCE INFORMATION MAS 3587F Contents, continued Page 17 17 17 17 18 19 19 19 24 24 25 25 26 26 27 27 28 28 29 29 29 30 30 31 31 32 32 32 32 40 41 42 42 42 43 49 50 50 50 53 53 53 53 53 53 53 Section 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.2. 3.2.1. 3.2.2. 3.3. 3.3.1. 3.3.1.1. 3.3.1.2. 3.3.1.3. 3.3.1.4. 3.3.1.5. 3.3.1.6. 3.3.1.7. 3.3.1.8. 3.3.1.9. 3.3.1.10. 3.3.1.11. 3.3.1.12. 3.3.1.13. 3.3.1.14. 3.3.1.15. 3.3.2. 3.3.3. 3.3.3.1. 3.3.3.2. 3.3.4. 3.3.5. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. Title I2C Interface General Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Run and Freeze Read Register (Code Ahex) Write Register (Code Bhex) Read D0 Memory (Code Chex) Short Read D0 Memory (Code C4hex) Read D1 Memory (Code Dhex) Short Read D1 Memory (Code D4hex) Write D0 Memory (Code Ehex) Short Write D0 Memory (Code E4hex) Write D1 Memory (Code Fhex) Short Write D1 Memory (Code F4hex) Clear SYNC Signal (Code 5hex) Default Read Fast Program Download Serial Program Download List of DSP Registers List of DSP Memory Cells Application Select and Running Application Specific Control Ancillary Data DSP Volume Control Audio Codec Access Protocol Write Codec Register Read Codec Register Codec Registers Basic MDB Configuration Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Reference Pins DC/DC Converters and Battery Voltage Supervision Oscillator Pins and Clocking Control Lines Parallel Interface Lines Micronas 3 MAS 3587F Contents, continued Page 54 54 54 54 54 54 54 54 55 55 56 58 58 59 62 63 64 66 68 69 70 71 72 76 77 79 80 82 Section 4.3.6.1. 4.3.7. 4.3.8. 4.3.9. 4.3.10. 4.3.11. 4.3.12. 4.3.13. 4.3.14. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.4. 4.6.5. 4.6.6. 4.7. 4.8. 5. Title PIO Handshake Lines Serial Input Interface (SDI) Serial Input Interface B (SDIB) Serial Output Interface (SDO) S/PDIF Input Interface S/PDIF Output Interface Analog Input Interfaces Analog Output Interfaces Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Digital Characteristics I2C Characteristics Serial (I2S) Input Interface Characteristics (SDI, SDIB) Serial Output Interface Characteristics (SDO) S/PDIF Input Characteristics S/PDIF Output Characteristics PIO as Parallel Input Interface: DMA Mode PIO as Parallel Output Interface: DMA Mode Analog Characteristics DC/DC Converter Characteristics Typical Performance Characteristics Typical Application in a Portable Player Recommended DC/DC Converter Application Circuit Data Sheet History ADVANCE INFORMATION 4 Micronas ADVANCE INFORMATION MAS 3587F 1.1. Features Firmware – MPEG 1/2 layer 3 encoder MPEG Layer 3 Audio Encoder/Decoder This data sheet applies to MAS 3587F version A1. 1. Introduction The MAS 3587F is a single-chip MPEG layer 3 audio encoder/decoder designed for use in memory-based recording/playback applications, e.g. MP3 record/playback equipment. The IC contains a DSP engine with embedded RAM and ROM. It provides flexible digital interfaces for serial and S/PDIF audio data input and output. Also integrated are power management functions .


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