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SY10E143 Dataheets PDF



Part Number SY10E143
Manufacturers Micrel Semiconductor
Logo Micrel Semiconductor
Description 9-BIT HOLD REGISTER
Datasheet SY10E143 DatasheetSY10E143 Datasheet (PDF)

Micrel, Inc. NOT RECOMMENDED FOR NEW DESIGNS 9-BIT HOLD REGISTER SY10E143 SY1S0YE10104E3143 SY100E143 FEATURES s 700MHz min. operating frequency s Extended 100E VEE range of –4.2V to –5.5V s 9 bits wide for byte-parity applications s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75kΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E143 s Available in 28-pin PLCC package BLOCK DIAGRAM D MUX D0 R D D1 MU.

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Micrel, Inc. NOT RECOMMENDED FOR NEW DESIGNS 9-BIT HOLD REGISTER SY10E143 SY1S0YE10104E3143 SY100E143 FEATURES s 700MHz min. operating frequency s Extended 100E VEE range of –4.2V to –5.5V s 9 bits wide for byte-parity applications s Asynchronous Master Reset s Dual clocks s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75kΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E143 s Available in 28-pin PLCC package BLOCK DIAGRAM D MUX D0 R D D1 MUX R D MUX D2 R D MUX D3 R D D4 MUX R D MUX D5 R D D6 MUX R D D7 MUX R D8 SEL CLK1 CLK2 MR MUX D R M9999-032006 [email protected] or (408) 955-1690 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 DESCRIPTION The SY10/100E143 are high-speed 9-bit hold registers designed for use in new, high-performance ECL systems. The E143 can hold current data or load new data. The nine inputs, D0-D8, accept parallel input data. The SEL (Select) control pin serves to determine the mode of operation; either HOLD or LOAD. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR. The E143 is designed for applications requiring highspeed registers, pipeline registers, synchronous operation, and is also suitable for byte-wide parity. PIN NAMES Pin D0-D8 SEL CLK1, CLK2 MR Q0-Q8 NC VCCO Function Parallel Data Inputs Mode Select Input Clock Inputs Master Reset Data Outputs No Connection VCC to Output Rev.: F Amendment: /0 1 Issue Date: March 2006 Micrel, Inc. SY10E143 SY100E143 PACKAGE/ORDERING INFORMATION MR CLK1 CLK2 VEE NC D0 D1 Ordering Information(1) SEL D8 D7 D6 D5 VCCO Q8 25 24 23 22 21 20 19 26 18 27 17 28 PLCC 16 1 TOP VIEW 15 2 J28-1 14 3 13 4 12 5 6 7 8 9 10 11 Q7 Q6 VCC Q5 VCCO Q4 Q3 D2 D3 D4 VCCO Q0 Q1 Q2 28-Pin PLCC (J28-1) Part Number SY10E143JC SY10E143JCTR(2) SY100E143JC SY100E143JCTR(2) SY10E143JZ(3) Package Type J28-1 J28-1 J28-1 J28-1 J28-1 SY10E143JZTR(2, 3) SY100E143JZ(3) J28-1 J28-1 SY100E143JZTR(2, 3) J28-1 Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Package Marking SY10E143JC Lead Finish Sn-Pb SY10E143JC Sn-Pb SY100E143JC Sn-Pb SY100E143JC Sn-Pb SY10E143JZ with Matte-Sn Pb-Free bar-line indicator SY10E143JZ with Matte-Sn Pb-Free bar-line indicator SY100E143JZ with Matte-Sn Pb-Free bar-line indicator SY100E143JZ with Matte-Sn Pb-Free bar-line indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. M9999-032006 [email protected] or (408) 955-1690 2 Micrel, Inc. TRUTH TABLE SEL L H MODE LOAD HOLD SY10E143 SY100E143 DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C TA = +25°C TA = +85°C Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IIH Input HIGH Current — — 150 — — 150 — — 150 IEE Power Supply Current 10E — 120 145 — 120 145 — 120 145 100E — 120 145 — 120 145 — 138 165 Unit µA mA Condition — — AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit fMAX Max. Toggle Frequency 700 900 — 700 900 — 700 900 — MHz tPD Propagation Delay to Output ps CLK 600 800 1000 600 800 1000 600 800 1000 MR 600 800 1000 600 800 1000 600 800 1000 tS Set-up Time D SEL 50 –100 — 50 –100 — 50 –100 — 300 150 — 300 150 — 300 150 — ps tH Hold Time D SEL 300 100 — 300 100 — 300 100 — 75 –150 — 75 –150 — 75 –150 — ps tRR Reset Recovery Time 900 700 — 900 700 — 900 700 — ps tPW Minimum Pulse Width CLK, MR 400 — — 400 — — 400 — — ps tskew Within-Device Skew — 75 — — 75 — — 75 — ps tr Rise/Fall Time tf 20% to 80% 300 525 800 300 525 800 Note: 1. Within-device skew is defined as identical transitions on similar paths through a device. 300 525 800 ps Condition — — — — — — 1 — M9999-032006 [email protected] or (408) 955-1690 3 Micrel, Inc. 28-PIN PLCC (J28-1) SY10E143 SY100E143 Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal in.


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