SY10E150

Micrel, Inc. 6-BIT D LATCH SY10E150 SY1S0YE10105E0150 SY100E150 FEATURES s 700ps max. propagation delay s Extended 100E VEE range of –4.2V to –5.5V s Differential outputs s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E150 s Available in 28-pin PLCC package BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 LEN1 LEN2 MR D R D R D R D R D R D R Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 DESCRIPTION The SY10/100E150 are 6-bit D latches with differential outputs designed for use in new, high- performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW. PIN NAMES Pin D0–D5 LEN1, LEN2 MR Q0–Q5 Q0–Q5 VCCO Function Data Inputs Latch Enables Master Reset True Outputs Inverting Outputs VCC to Output M9999-032006 [email protected] or (408) 955-1690 1 Rev.: F Amendment: /0 Issue Date: March 2006 Micrel, Inc. SY10E150 SY100E150 PACKAGE/ORDERING INFORMATION Ordering Information(1) MR LEN2 LEN1 NC VCCO Q5 Q5 Part Number Package Operating Type Range Package Marking Lead Finish 25 24 23 22 21 20 19 SY10E150JC D5 D4 D3 VEE D2 26 27 28 1 2 PLCC TOP VIEW J28-1 18 Q4 SY10E150JCTR(2) 17 Q4 16 VCC SY100E150JC 15 Q3 SY100E150JCTR(...