SY10E156

3-BIT 4:1 MUX-LATCH SY10E156 SY100E156 FEATURES s s s s s s s 900ps max. D to output Extended 100E VEE range of –4.2V to –5.5V 800ps max. LEN to output Differential outputs Asynchronous Master Reset Dual latch enables Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75KΩ input pulldown resistors s Fully compatible with Motorola MC10E/100E156 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latches. When both LEN1 and LEN 2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the Select (SEL0, SEL1) signals which select one of the four bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to take all outputs to a logic LOW. BLOCK DIAGRAM PIN CONFIGURATION D2b D2a VCCO D1b D1a SEL0 SEL1 MR D0a D0b D0c D0d 4:1 MUX D E N R Q0 Q0 26 27 28 1 2 3 4 25 24 23 22 21 20 19 18 17 D2d D2c Q2 Q2 VCC Q1 Q1 VCCO Q0 D1a D1b D1c D1d D 4:1 MUX E N R Q1 Q1 VEE LEN1 LEN2 D1c PLCC TOP VIEW J28-1 16 15 14 13 12 5 6 7 8 9 10 11 D2a D2b D2c D2d SE...