Document
ST24C08, ST25C08 ST24W08, ST25W08
8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE: – 3V to 5.5V for ST24x08 versions – 2.5V to 5.5V for ST25x08 versions HARDWARE WRITE CONTROL VERSIONS: ST24W08 and ST25W08 PROGRAMMABLE WRITE PROTECTION TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE BYTE and MULTIBYTE WRITE (up to 8 BYTES) PAGE WRITE (up to 16 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD/LATCH UP PERFORMANCES
8 1
PSDIP8 (B) 0.25mm Frame
8 1
SO8 (M) 150mil Width
Figure 1. Logic Diagram
DESCRIPTION This specification covers a range of 8 Kbits I2C bus EEPROM products, the ST24/25C08 and the ST24/25W08. In the text, products are referred to as ST24/25x08, where "x" is: "C" for Standard version and "W" for Hardware Write Control version.
VCC
E PRE SCL ST24x08 ST25x08
SDA
Table 1. Signal Names
PRE E SDA SCL MODE WC VCC VSS Write Protect Enable Chip Enable Input Serial Data Address Input/Output Serial Clock Multibyte/Page Write Mode (C version) Write Control (W version) Supply Voltage Ground
MODE/WC*
VSS
AI00860E
Note: WC signal is only available for ST24/25W08 products.
February 1999
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ST24/25C08, ST24/25W08
Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections
ST24x08 ST25x08 PRE NC E VSS 1 2 3 4 8 7 6 5
AI00861E
ST24x08 ST25x08 VCC MODE/WC SCL SDA PRE NC E VSS 1 2 3 4 8 7 6 5
AI01073E
VCC MODE/WC SCL SDA
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) Electrostatic Discharge Voltage (Machine model)
(3) (2)
Value –40 to 125 –65 to 150
Unit °C °C °C V V V V
(SO8 package) (PSDIP8 package)
40 sec 10 sec
215 260 –0.6 to 6.5 –0.3 to 6.5 4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). 3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d) The ST24/25x08 are 8 Kbit electrically erasable programmable memories (EEPROM), organized as 4 blocks of 256 x8 bits. They are manufactured in STMicroelectronics’s Hi-Endurance Advanced CMOS technology which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. Both Plastic Dual-in-Line and Plastic Small Outline packages are available. The memories are compatible with the I2C standard, two wire serial interface which uses a bi-direc-
tional data bus and serial clock. The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. This is used together with 1 chip enable input (E) so that up to 2 x 8K devices may be attached to the I2C bus and selected individually. The memories behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.
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ST24/25C08, ST24/25W08
Table 3. Device Select Code
Device Code Bit Device Select
Note: The MSB b7 is sent first.
Chip Enable b4 0 b3 E b2 A9
Block Select b1 A8
RW b0 RW
b7 1
b6 0
b5 1
Table 4. Operating Modes (1)
Mode Current Address Read Random Address Read Sequential Read Byte Write Multibyte Write Page Write
(2)
RW bit ’1’ ’0’ ’1’ ’1’ ’0’ ’0’ ’0’
MODE X X X X VIH VIL
Bytes 1 1 1 to 1024 1 8 16
Initial Sequence START, Device Select, RW = ’1’ START, Device Select, RW = ’0’, Address, reSTART, Device Select, RW = ’1’ Similar to Current or Random Mode START, Device Select, RW = ’0’ START, Device Select, RW = ’0’ START, Device Select, RW = ’0’
Notes: 1. X = VIH or VIL 2. Multibyte Write not available in ST24/25W08 versions.
When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is impl.