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MN673274 Dataheets PDF



Part Number MN673274
Manufacturers Panasonic
Logo Panasonic
Description Signal-Processing LSI for Multimedia Camera
Datasheet MN673274 DatasheetMN673274 Datasheet (PDF)

Video Camera LSI MN673274 Signal-Processing IC for Multipurpose Cameras s Overview The MN673274 is designed for surveillance and PC input cameras. In addition to the basic functions of luminance signal and chrominance signal processing, it also integrates microcontroller functions (ALC, AWB, and AGC) and SSG, CG, and I2C-bus circuits on a single chip. s Features • Input: Analog signal (A/D converter input) • Output: Digital output YUV signal: 8 bits Analog outputs Y signal C signal Composite v.

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Video Camera LSI MN673274 Signal-Processing IC for Multipurpose Cameras s Overview The MN673274 is designed for surveillance and PC input cameras. In addition to the basic functions of luminance signal and chrominance signal processing, it also integrates microcontroller functions (ALC, AWB, and AGC) and SSG, CG, and I2C-bus circuits on a single chip. s Features • Input: Analog signal (A/D converter input) • Output: Digital output YUV signal: 8 bits Analog outputs Y signal C signal Composite video output RGB outputs • Operating supply voltage: 3.3 V ± 0.3 V • Operating frequency: 9.5 MHz to 28.7 MHz • Main functions • 10-bit A/D converter • 10-bit D/A converter • 2-channel 8-bit D/A converter • Support for analog AGC (NN2038, NN2039) • CG and SSG functions • 510H and 768H (Supports NTSC and PAL ) • Supports progressive scan readout CCDs with complementary color filters for VGA • Supports black-and-white CCD signal processing • CCD white defect/black defect correction circuit • Maximum digital AGC gain: 24 dB • Left/right reversing function • Variable gamma correction (γ = 0.3 to 1) • ZV port conforming mode, BT656 conforming mode • External synchronization support: HD/VD, VD2, Sync., LL mode • On-chip I2C-bus circuit • ELC/AGC (Also supports external AGC) • Two-mode white balance (manual/ATW) with ATW lock function • Automatic OB correction function s Applications • Surveillance cameras, PC cameras 1 MN673274 s Block Diagram Video Camera LSI YUVOE Y VIN 10-bit A/D AGC Y signal processing Y/C MPX 10-bit D/A C C signal processing ENC 8-bit D/A YUV0 to 7 Composite Y/C video signal output RGB CNV White balance gain Carrier signal YLPF Digital AGC control ALC ATN Sub control BLK CSYNC (2-ch) Y output, G C output, B Horizontal drive pulse output Read and write of registers for each circuit block Data WE RE SCL SDA PWM0 PWM1 PWM2 PWM3 CG I2C-bus control PWM PWM PWM PWM Vertical drive Sync system pulse output FCK 2FCK FCKO 2FCKO 2 SSG YUVOE 2 Video Camera LSI s Pin Arrangement FCK2O FCKO VSS3 VDD3 YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 PWM3 PWM2 PWM1 PWM0 VSS2 VDD2 A2 A1 A0 SCL SDA RESET CCDSEL2 CCDSEL1 CCDSEL0 TEST0 TEST1 TEST2 TEST3 TEST4 COIN OBCTL EXTAGC IRIS ALCELC ATWLOCK APGAIN BLCSW DIN8 DIN7 DIN6 DIN5 DIN4 VDD4 VSS4 DIN3 DIN2 DIN1 DIN0 DS2 DS1 TESTDC2 N.C. R N.C. TGVDD TGVSS N.C. H2 N.C. H1 N.C. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N.C. V4 V3 VSS5 VDD5 V2 N.C. V1 N.C. SUB N.C. CH2 N.C. CH1 OSCCNT CXIN CXOUT OSCVDD OSCVSS OSCSEL WHD FVD FWHD CPOB PBLK HCLR LLDET FLC VDD1 VSS1 EXTIN0 EXTIN1 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MN673274 VIN VREFL VREFML ADVDD ADVSS VREFM VREFHM VREFH VREF23 IREF23 COMP23 BSIG DAVSS1 DAVDD1 RSIG VREF1 IREF1 COMP1 GSIG DAVSS2 DAVDD2 VCXO LPFI FVR MINTEST SCANT HREFCBLK VCSYNCVD YUVOE NTPL PCO EXTMOD (TOP VIEW) 3 MN673274 s Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin Name N.C. V4 V3 VSS5 VDD5 V2 N.C. V1 N.C. SUB N.C. CH2 N.C. CH1 OSCCNT CXIN CXOUT OSCVDD OSCVSS OSCSEL WHD FVD FWHD CPOB PBLK HCLR LLDET I/O  O O VSS VDD O  O  O  O  O O I O VDD VSS I O O O O O O I V1 charge pulse Oscillator control test V3 charge pulse  Vertical exclusion pulse  φ V1 charge pulse  φ V4 charge pulse φ V3 charge pulse Digital system ground Digital system power supply (3.3 V) φ V2 charge pulse  Description  Video Camera LSI Synchronization oscillator connection (crystal oscillator) Synchronization oscillator connection (crystal oscillator) Oscillator cell power supply Oscillator cell ground Source oscillator 2FCK/4FCK switching WHD signal with a normal phase to Sync VD signal with a normal phase to Sync WHD for CG drive A/D converter input signal clamping pulse/ D/A converter output clamping pulse Pre-blanking pulse Horizontal reference signal Power supply synchronization switching high: LL synchronization Low: internal synchronization, 28 29 30 31 32 33 FLC VDD1 VSS1 EXTIN0 EXTIN1 EXTMOD I VDD VSS I I I Flicker correction (pulled-up input) High: flicker correction on Digital system power supply (3.3 V) Digital system ground External synchronization input 1 External synchronization input 2 Surveillance/automotive mode switching (pulled-up input) High: automotive mode (HDVD/Sync synchronization mode) 34 35 4 PCO NTPL O I Phase comparator output NTSC/PAL switching Low: NTSC, high: PAL (pulled-down input) Video Camera LSI s Pin Descriptions (continued) Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name YUVOE VCSYNCVD HREFCBLK SCANT MINTEST FVR LPFI VCXO DAVDD2 DAVSS2 GSIG COMP1 IREF1 VREF1 RSIG DAVDD1 .


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