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MT9046 Dataheets PDF



Part Number MT9046
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description T1/E1 System Synchronizer with Holdover
Datasheet MT9046 DatasheetMT9046 Datasheet (PDF)

MT9046 T1/E1 System Synchronizer with Holdover Data Sheet Features • Supports AT&T TR62411 and Bellcore GR-1244CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accuracy of 0.2.

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MT9046 T1/E1 System Synchronizer with Holdover Data Sheet Features • Supports AT&T TR62411 and Bellcore GR-1244CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accuracy of 0.2 PPM Holdover indication Attenuates wander from 1.9 Hz Fast lock mode Provides Time Interval Error (TIE) correction Accepts reference inputs from two independent sources JTAG Boundary Scan OSCi OSCo TCLR April 2004 Ordering Information MT9046AN 48 pin SSOP -40° C to +85° C • • • Applications • • Synchronization and timing control for Customer Premises Equipment (CPE) ST-BUS clock and frame pulse sources • • • • • • • • Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connectivity during temporary synchronization interruptions. LOCK VDD VSS Master Clock TCK TDI TMS TRST TDO PRI SEC IEEE 1149.1a TIE Corrector Circuit Virtual Reference DPLL Output Interface Circuit Reference Select MUX Selected Reference TIE Corrector Enable Reference Select State Select Input Impairment Monitor State Select C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP RSEL Control State Machine Feedback Frequency Select MUX MS1 MS2 RST HOLDOVER PCCi FLOCK FS1 FS2 Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003 - 2004, Zarlink Semiconductor Inc. All Rights Reserved. MT9046 Data Sheet The MT9046 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048 MHz, 1.544 MHz, or 8 kHz input reference. The MT9046 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, and Stratum 4 and ETSI ETS 300 011 interfaces. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range, phase change slope frequency and MTIE requirements for these specifications. VSS RST TCLR NC SEC PRI Vdd OSCo OSCi Vss F16o F0o RSP TSP F8o C1.5o Vdd LOCK C2o C4o C19o FLOCK Vss IC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 TMS TCK TRST TDI TDO NC IC FS1 FS2 IC RSEL MS1 MS2 Vdd IC IC NC Vss PCCi HOLDOVER Vdd C6o C16o C8o Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. MT9046 Pin Description Pin # 1,10, 23,31 2 Name VSS RST Ground. 0 Volts. (Vss pads). Description Data Sheet Reset (Input). A logic low at this input resets the MT9046. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RST pin should be held low for a minimum of 300 ns. While the RST pin is low, all frame pulses except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RST, TSP, C6o and C16o are at logic low during reset. The C19o is free-running during reset. Following a reset, the input reference source, output clocks and frame pulses are phase aligned as shown in Figure 13. TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase as shown in Figure 13. The TCLR pin should be held low for a minimum of 300 ns. This pin is internally pulled down to VSS. No Connection. Leave open Circuit Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be used. The selection of the input reference is based upon the MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to VDD. Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to VDD. Positive Supply Voltage. +3.3 VDC nominal. Oscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi, see Figure 9. For clock oscillator operation, this pin is left unconnected, see Figure 8. Oscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is connected to a clock source, see Figure 8. Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61 ns active low framing pulse, which marks the beginnin.


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