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MT90503 Dataheets PDF



Part Number MT90503
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description 2048VC AAL1 SAR
Datasheet MT90503 DatasheetMT90503 Datasheet (PDF)

MT90503 2048VC AAL1 SAR Data Sheet Features • AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services Interoperability Specifications" (Nx64 Basic Service, DS1 Nx64 Service with CAS, and E1 Nx64 Service with CAS) Two UTOPIA ports (Level 2, 16-bit, 50 MHz) with loopback function for dual fibre ring applications Third UTOPIA port.

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MT90503 2048VC AAL1 SAR Data Sheet Features • AAL1 Segmentation and Reassembly device capable of simultaneously processing up to 2048 bidirectional VCs AAL1 cell format for "Structured DS1/E1 N x 64kbps Service" as per ATM Forum AF-VTOA0078.000 "Circuit Emulation Services Interoperability Specifications" (Nx64 Basic Service, DS1 Nx64 Service with CAS, and E1 Nx64 Service with CAS) Two UTOPIA ports (Level 2, 16-bit, 50 MHz) with loopback function for dual fibre ring applications Third UTOPIA port for connection to an external AAL5 SAR processor, or for chaining multiple MT90503 or other SAR or IMA devices Flexible aggregation capabilities (Nx64) to allow any combination of 64 Kbps TDM bus provides 32 bidirectional serial TDM streams at 2.048, 4.096, or 8.192 Mbps for up to 4096 TDM 64 Kbps channels Compatible with H.100 and H.110 interfaces Ordering Information MT90503AG 503 Pin PBGA December 2004 • For temperature range, see page 207. • • TDM to ATM transmission latency less than 250 µs Support for clock recovery - Adaptive Clock Recovery, Synchronous Residual Time Stamp (SRTS) or external Support master and slave TDM bus clock operation 8- or 16-bit microprocessor port, configurable to Motorola or Intel timing Master clock rate up to 80 MHz Single power supply device (3.3V) IEEE 1149 (JTAG) interface • • • • • • • • • • Control Memory (external SSRAM) Address bus and 8- or 16-bit Data bus Control Memory Controller CPU Module Registers H.100/ H.110 TDM Bus 4096 x 64kbps TX_SAR Module RX_SAR Module UTOPIA Module Port A Port B RXA Port TXA Port RXB Port TXB Port RXC Port TXC Port TDM Module Data Memory Controller Clock Recovery Submodule Port C Boundary Scan Logic JTAG Interface Clock Signals Data Memory (external SSRAM) Figure 1 - Functionl Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. MT90503 Description Data Sheet The MT90503 is an AAL1 SAR, which offers a highly integrated solution for interfacing telecom bus-based systems with ATM networks. The device has the capability of simultaneously processing 2048 bidirectional channels of 64 kbps. The MT90503 can be connected directly to an H.100 or H.110 compatible bus. The device also offers the capability of using Channel Associated Signalling (CAS) to support Circuit Emulation Service (CES) for Structured Data Transfer (SDT). The interface to the TDM port is provided by a TDM bus, which consists of 32 bidirectional serial TDM data streams at 2.048, 4.096, or 8.192 Mbps, therefore allowing for 2048 bidirectional TDM channels operating at 64 kbps. This TDM bus is compatible with the ECTF H.100 and H.110 specifications. The interface to the ATM domain is provided by three UTOPIA ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Port A can also be configured as Level 2 M-PHY mode. Applications • • • • • • • • ATM Access and Multiplexing Equipment Switching Platforms that provide internetworking between TDM and ATM ATM Edge Switches ATM uplink for expansion of COs, PBXs, or open switching platforms using an adjunct ATM switch Integrated Digital Loop Carrier (IDLC) SONET or SDH Add and Drop Multiplexers (ADM) Next Generation Digital Loup Carrier (NGDIC) Digital Subscriber Line Access Multiplexer DSLAM with Gateway Switching Feature • Cells coming in from any of the UTOPIA ports can be switched to any other port. The user has the option to change the VPI and VCI fields. PURCHASE OF THIS PRODUCT DOES NOT GRANT THE PURCHASER ANY RIGHTS UNDER PATENT NO. 5,260,978. USE OF THIS PRODUCT OR ITS RE-SALE AS A COMPONENT OF ANOTHER PRODUCT MAY REQUIRE A LICENSE UNDER THE PATENT WHICH IS AVAILABLE FROM TELCORDIA TECHNOLOGIES, INC., 445 SOUTH STREET , MORRISTOWN, NEW JERSEY 07960. ZARLINK ASSUMES NO RESPONSIBILITY OR LIABILITY THAT MAY RESULT FROM ITS CUSTOMERS' USE OF ZARLINK PRODUCTS WITH RESPECT TO THIS PATENT. IN PARTICULAR, ZARLINK'S PATENT INDEMNITY IN ITS TERMS AND CONDITIONS OF SALES WHICH ARE SET OUT IN ITS SALES ACKNOWLEDGEMENTS AND INVOICES DOES NOT APPLY TO THIS PATENT. 2 Zarlink Semiconductor Inc. MT90503 Data Sheet PSTN SDT Traffic T3/E3 T3/E3 LIU M13 MUX Octal T1/E1 Framers MT9072 2048 channels AALI SAR MT90503 Clock Oscillator Digital PLL MT9045 ATM UTOPIA Bus ATM Network Uplink OC-12 Framers & ATM Cell Access Stratum 3 Timing Card PSTN UDT Traffic T1/E1 Circuit Emulation Services T1/E1 LIU 28 port AAL1 SAR MT90528 Optical Interface & Drivers Stratum 3 Timing Card Clock Oscillator Digital PLL MT9045 Traffic Management & Switching ATM Traffic T1/E1 IMA Uplink T1/E1 Framers MT9076 Octal/IMA MT90220 Figure 2 - ATM Switch Application 3 Zarlink Semiconductor Inc. MT90503 Table of Contents Data Sheet 1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..


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