MT9075A

MT9075A E1 Single Chip Transceiver Preliminary Information Features Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package Selectable bit rate data link access with optional S a bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1) Enhanced performance monitoring and programmable error insertion functions Low jitter DPLL for clock generation Operating under synchronized or free run mode Two-frame receive elastic buffer with controlled slip direction indication Selectable transmit or receive jitter attenuator Intel or Motorola non-multiplexed parallel microprocessor interface CRC-4 updating algorithm for intermediate path points of a message-based data link application ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling. E1 add/drop multiplexers and channel banks CO and PBX equipment interfaces Primary Rate ISDN nodes Digital Cross-connect Systems (DCS) ISSUE 5 December 1997 Ordering Information MT9075AP 68Pin PLCC MT9075AL 100 Pin MQFP -40°C to 85°C Description The MT9075A is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line. The MT9075A meets or supports the latest ITU-T Recom...